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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 13:27:45 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-05-17 16:23:06 +0200 |
commit | a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1 (patch) | |
tree | fe87198c6cc02e54d3131d087d2b9f7c3e96c689 /dts/Bindings/gpio/rockchip,gpio-bank.yaml | |
parent | ba9de18c5f211678f5d0f67a0758c632ab774cca (diff) | |
download | barebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.gz barebox-a5a4c1d5a3c4f89059fb612b5786ec8b61b959f1.tar.xz |
dts: update to v5.13-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/gpio/rockchip,gpio-bank.yaml')
-rw-r--r-- | dts/Bindings/gpio/rockchip,gpio-bank.yaml | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/dts/Bindings/gpio/rockchip,gpio-bank.yaml b/dts/Bindings/gpio/rockchip,gpio-bank.yaml new file mode 100644 index 0000000000..d993e002ce --- /dev/null +++ b/dts/Bindings/gpio/rockchip,gpio-bank.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip GPIO bank + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,gpio-bank + - rockchip,rk3188-gpio-bank0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl: pinctrl { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; |