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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-10-15 10:55:58 +0200 |
commit | 2036f2866753a28b2783ad6dc78a40ca5345e6d8 (patch) | |
tree | 468b1c17b06a2377c5f8e6d711d8f3187f60667f /dts/Bindings/gpio/sgpio-aspeed.txt | |
parent | 785f926d4527184194b6424bc39ce367e2cea7d8 (diff) | |
download | barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.gz barebox-2036f2866753a28b2783ad6dc78a40ca5345e6d8.tar.xz |
dts: update to v5.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/gpio/sgpio-aspeed.txt')
-rw-r--r-- | dts/Bindings/gpio/sgpio-aspeed.txt | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/dts/Bindings/gpio/sgpio-aspeed.txt b/dts/Bindings/gpio/sgpio-aspeed.txt new file mode 100644 index 0000000000..d4d83916c0 --- /dev/null +++ b/dts/Bindings/gpio/sgpio-aspeed.txt @@ -0,0 +1,45 @@ +Aspeed SGPIO controller Device Tree Bindings +-------------------------------------------- + +This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full +featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to +support the following options: +- Support interrupt option for each input port and various interrupt + sensitivity option (level-high, level-low, edge-high, edge-low) +- Support reset tolerance option for each output port +- Directly connected to APB bus and its shift clock is from APB bus clock + divided by a programmable value. +- Co-work with external signal-chained TTL components (74LV165/74LV595) + +Required properties: + +- compatible : Should be one of + "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio" +- #gpio-cells : Should be 2, see gpio.txt +- reg : Address and length of the register set for the device +- gpio-controller : Marks the device node as a GPIO controller +- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt +- interrupt-controller : Mark the GPIO controller as an interrupt-controller +- ngpios : number of GPIO lines, see gpio.txt + (should be multiple of 8, up to 80 pins) +- clocks : A phandle to the APB clock for SGPM clock division +- bus-frequency : SGPM CLK frequency + +The sgpio and interrupt properties are further described in their respective +bindings documentation: + +- Documentation/devicetree/bindings/gpio/gpio.txt +- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + + Example: + sgpio: sgpio@1e780200 { + #gpio-cells = <2>; + compatible = "aspeed,ast2500-sgpio"; + gpio-controller; + interrupts = <40>; + reg = <0x1e780200 0x0100>; + clocks = <&syscon ASPEED_CLK_APB>; + interrupt-controller; + ngpios = <8>; + bus-frequency = <12000000>; + }; |