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authorSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
commit3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 (patch)
treeeb5a7bfce811d20e58dd0eb1add0f6cf0e6b86e0 /dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
parent81ceab95360295cef146e89a1cd1cd5e590aa75e (diff)
downloadbarebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.gz
barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.xz
dts: update to v5.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml')
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diff --git a/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/dts/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
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@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ZynqMP Mode Pin GPIO controller
+
+description:
+ PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
+ GPIO controller with configurable from numbers of pins (from 0 to 3 per
+ PS_MODE). Every pin can be configured as input/output.
+
+maintainers:
+ - Piyush Mehta <piyush.mehta@xilinx.com>
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-gpio-modepin
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+required:
+ - compatible
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ zynqmp-firmware {
+ gpio {
+ compatible = "xlnx,zynqmp-gpio-modepin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+...