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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-09 14:49:17 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 09:37:13 +0100 |
commit | f826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch) | |
tree | dd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/Bindings/iio/adc | |
parent | 0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff) | |
download | barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz |
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/iio/adc')
-rw-r--r-- | dts/Bindings/iio/adc/adi,ad7768-1.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/lltc,ltc2496.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/qcom,spmi-vadc.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/st,stm32-adc.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/x-powers,axp209-adc.yaml | 12 | ||||
-rw-r--r-- | dts/Bindings/iio/adc/xilinx-xadc.txt | 49 |
7 files changed, 54 insertions, 15 deletions
diff --git a/dts/Bindings/iio/adc/adi,ad7768-1.yaml b/dts/Bindings/iio/adc/adi,ad7768-1.yaml index 924477dfb8..a85a28145e 100644 --- a/dts/Bindings/iio/adc/adi,ad7768-1.yaml +++ b/dts/Bindings/iio/adc/adi,ad7768-1.yaml @@ -40,6 +40,7 @@ properties: ADC reference voltage supply adi,sync-in-gpios: + maxItems: 1 description: Enables synchronization of multiple devices that require simultaneous sampling. A pulse is always required if the configuration is changed @@ -76,6 +77,7 @@ patternProperties: properties: reg: + maxItems: 1 description: | The channel number. diff --git a/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml b/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml index 7f534a933e..a726b6c2ab 100644 --- a/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml +++ b/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml @@ -23,6 +23,7 @@ properties: maxItems: 1 clocks: + maxItems: 1 description: Input clock used to derive the sample clock. Expected to be the SoC's APB clock. diff --git a/dts/Bindings/iio/adc/lltc,ltc2496.yaml b/dts/Bindings/iio/adc/lltc,ltc2496.yaml index 2716d4e953..0bd2fc0356 100644 --- a/dts/Bindings/iio/adc/lltc,ltc2496.yaml +++ b/dts/Bindings/iio/adc/lltc,ltc2496.yaml @@ -20,7 +20,7 @@ properties: description: Power supply for the reference voltage reg: - description: spi chipselect number according to the usual spi bindings + maxItems: 1 spi-max-frequency: description: maximal spi bus frequency supported diff --git a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml index 95cc705b96..74a4a9d957 100644 --- a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml @@ -68,6 +68,7 @@ patternProperties: properties: reg: + maxItems: 1 description: | ADC channel number. See include/dt-bindings/iio/qcom,spmi-vadc.h diff --git a/dts/Bindings/iio/adc/st,stm32-adc.yaml b/dts/Bindings/iio/adc/st,stm32-adc.yaml index 517e32976c..a58334c3bb 100644 --- a/dts/Bindings/iio/adc/st,stm32-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-adc.yaml @@ -41,6 +41,8 @@ properties: maxItems: 2 clocks: + minItems: 1 + maxItems: 2 description: | Core can use up to two clocks, depending on part used: - "adc" clock: for the analog circuitry, common to all ADCs. diff --git a/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml b/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml index 5ccbb1f819..e759a5da70 100644 --- a/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml +++ b/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml @@ -46,10 +46,14 @@ description: | properties: compatible: - enum: - - x-powers,axp209-adc - - x-powers,axp221-adc - - x-powers,axp813-adc + oneOf: + - const: x-powers,axp209-adc + - const: x-powers,axp221-adc + - const: x-powers,axp813-adc + + - items: + - const: x-powers,axp803-adc + - const: x-powers,axp813-adc "#io-channel-cells": const: 1 diff --git a/dts/Bindings/iio/adc/xilinx-xadc.txt b/dts/Bindings/iio/adc/xilinx-xadc.txt index e0e0755cab..f42e180783 100644 --- a/dts/Bindings/iio/adc/xilinx-xadc.txt +++ b/dts/Bindings/iio/adc/xilinx-xadc.txt @@ -1,13 +1,22 @@ Xilinx XADC device driver -This binding document describes the bindings for both of them since the -bindings are very similar. The Xilinx XADC is a ADC that can be found in the -series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. -Currently two different frontends for the DRP interface exist. One that is only -available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The -other one is available on all series 7 platforms and is a softmacro with a AXI -interface. This binding document describes the bindings for both of them since -the bindings are very similar. +This binding document describes the bindings for the Xilinx 7 Series XADC as well +as the UltraScale/UltraScale+ System Monitor. + +The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx. +The XADC has a DRP interface for communication. Currently two different +frontends for the DRP interface exist. One that is only available on the ZYNQ +family as a hardmacro in the SoC portion of the ZYNQ. The other one is available +on all series 7 platforms and is a softmacro with a AXI interface. This binding +document describes the bindings for both of them since the bindings are very +similar. + +The Xilinx System Monitor is an ADC that is found in the UltraScale and +UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for +communication. Xilinx provides a standard IP core that can be used to access the +System Monitor through an AXI interface in the FPGA fabric. This IP core is +called the Xilinx System Management Wizard. This document describes the bindings +for this IP. Required properties: - compatible: Should be one of @@ -15,11 +24,14 @@ Required properties: configuration interface to interface to the XADC hardmacro. * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to interface to the XADC hardmacro. + * "xlnx,system-management-wiz-1.3": When using the + Xilinx System Management Wizard fabric IP core to access the + UltraScale and UltraScale+ System Monitor. - reg: Address and length of the register set for the device - interrupts: Interrupt for the XADC control interface. - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, - when using the AXI-XADC pcore this must be the clock that provides the - clock to the AXI bus interface of the core. + when using the axi-xadc or the axi-system-management-wizard this must be + the clock that provides the clock to the AXI bus interface of the core. Optional properties: - xlnx,external-mux: @@ -110,3 +122,20 @@ Examples: }; }; }; + + adc@80000000 { + compatible = "xlnx,system-management-wiz-1.3"; + reg = <0x80000000 0x1000>; + interrupts = <0 81 4>; + interrupt-parent = <&gic>; + clocks = <&fpga1_clk>; + + xlnx,channels { + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + xlnx,bipolar; + }; + }; + }; |