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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:29:57 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:29:57 +0200 |
commit | a4f4bc65b33164eb8c19bcff9834cc87bcc845bb (patch) | |
tree | ef97762be5b614f160e9affddd1bbbec43c007dc /dts/Bindings/interrupt-controller/al,alpine-msix.txt | |
parent | 83e61900b02965d01f0885e2db2077df35be7f56 (diff) | |
download | barebox-a4f4bc65b33164eb8c19bcff9834cc87bcc845bb.tar.gz barebox-a4f4bc65b33164eb8c19bcff9834cc87bcc845bb.tar.xz |
dts: update to v4.6-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/al,alpine-msix.txt')
-rw-r--r-- | dts/Bindings/interrupt-controller/al,alpine-msix.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/al,alpine-msix.txt b/dts/Bindings/interrupt-controller/al,alpine-msix.txt new file mode 100644 index 0000000000..f6f1c14bf9 --- /dev/null +++ b/dts/Bindings/interrupt-controller/al,alpine-msix.txt @@ -0,0 +1,26 @@ +Alpine MSIX controller + +See arm,gic-v3.txt for SPI and MSI definitions. + +Required properties: + +- compatible: should be "al,alpine-msix" +- reg: physical base address and size of the registers +- interrupt-parent: specifies the parent interrupt controller. +- interrupt-controller: identifies the node as an interrupt controller +- msi-controller: identifies the node as an PCI Message Signaled Interrupt + controller +- al,msi-base-spi: SPI base of the MSI frame +- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 + +Example: + +msix: msix { + compatible = "al,alpine-msix"; + reg = <0x0 0xfbe00000 0x0 0x100000>; + interrupt-parent = <&gic>; + interrupt-controller; + msi-controller; + al,msi-base-spi = <160>; + al,msi-num-spis = <160>; +}; |