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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-06 08:07:28 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-06-06 08:07:28 +0200 |
commit | bb2de9a333d17bb1b048ad208002501226b83f03 (patch) | |
tree | 8ef2e876ba43af235c45cb2280885e9c67ba5548 /dts/Bindings/interrupt-controller/arm,nvic.txt | |
parent | 79e6629b02fb3a296b5dc70f16dec0f8d415ccf8 (diff) | |
download | barebox-bb2de9a333d17bb1b048ad208002501226b83f03.tar.gz barebox-bb2de9a333d17bb1b048ad208002501226b83f03.tar.xz |
dts: update to v4.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/arm,nvic.txt')
-rw-r--r-- | dts/Bindings/interrupt-controller/arm,nvic.txt | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/arm,nvic.txt b/dts/Bindings/interrupt-controller/arm,nvic.txt new file mode 100644 index 0000000000..386ab37a38 --- /dev/null +++ b/dts/Bindings/interrupt-controller/arm,nvic.txt @@ -0,0 +1,36 @@ +* ARM Nested Vector Interrupt Controller (NVIC) + +The NVIC provides an interrupt controller that is tightly coupled to +Cortex-M based processor cores. The NVIC implemented on different SoCs +vary in the number of interrupts and priority bits per interrupt. + +Main node required properties: + +- compatible : should be one of: + "arm,v6m-nvic" + "arm,v7m-nvic" + "arm,v8m-nvic" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a <u32> and the value shall be 2. + + The 1st cell contains the interrupt number for the interrupt type. + + The 2nd cell is the priority of the interrupt. + +- reg : Specifies base physical address(s) and size of the NVIC registers. + This is at a fixed address (0xe000e100) and size (0xc00). + +- arm,num-irq-priority-bits: The number of priority bits implemented by the + given SoC + +Example: + + intc: interrupt-controller@e000e100 { + compatible = "arm,v7m-nvic"; + #interrupt-cells = <2>; + #address-cells = <1>; + interrupt-controller; + reg = <0xe000e100 0xc00>; + arm,num-irq-priority-bits = <4>; + }; |