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authorSascha Hauer <s.hauer@pengutronix.de>2015-12-08 07:33:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-12-10 08:48:39 +0100
commita05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch)
tree69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
parent48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff)
downloadbarebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt')
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt25
1 files changed, 24 insertions, 1 deletions
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
index 7da578d..2d6c8bb 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -5,9 +5,14 @@ The BCM2835 contains a custom top-level interrupt controller, which supports
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence naming of this binding.
+The BCM2836 contains the same interrupt controller with the same
+interrupts, but the per-CPU interrupt controller is the root, and an
+interrupt there indicates that the ARMCTRL has an interrupt to handle.
+
Required properties:
-- compatible : should be "brcm,bcm2835-armctrl-ic"
+- compatible : should be "brcm,bcm2835-armctrl-ic" or
+ "brcm,bcm2836-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
@@ -20,6 +25,12 @@ Required properties:
The 2nd cell contains the interrupt number within the bank. Valid values
are 0..7 for bank 0, and 0..31 for bank 1.
+Additional required properties for brcm,bcm2836-armctrl-ic:
+- interrupt-parent : Specifies the parent interrupt controller when this
+ controller is the second level.
+- interrupts : Specifies the interrupt on the parent for this interrupt
+ controller to handle.
+
The interrupt sources are as follows:
Bank 0:
@@ -102,9 +113,21 @@ Bank 2:
Example:
+/* BCM2835, first level */
intc: interrupt-controller {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
+
+/* BCM2836, second level */
+intc: interrupt-controller {
+ compatible = "brcm,bcm2836-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&local_intc>;
+ interrupts = <8>;
+};