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authorSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
commitbfbf18d991756858337f7700e8ff0a6f0dc31afc (patch)
treecf3568de4fdff1891e277507f08f49a871682706 /dts/Bindings/interrupt-controller/marvell,armada-8k-pic.txt
parent834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff)
downloadbarebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz
barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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+Marvell Armada 7K/8K PIC Interrupt controller
+---------------------------------------------
+
+This is the Device Tree binding for the PIC, a secondary interrupt
+controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
+typically connected to the GIC as the primary interrupt controller.
+
+Required properties:
+- compatible: should be "marvell,armada-8k-pic"
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: the number of cells to define interrupts on this
+ controller. Should be 1
+- reg: the register area for the PIC interrupt controller
+- interrupts: the interrupt to the primary interrupt controller,
+ typically the GIC
+
+Example:
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };