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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-09-12 10:51:16 +0200 |
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| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-09-12 10:51:16 +0200 |
| commit | 419db1f984f94aaa657f6c2c976afa8fcaecc42d (patch) | |
| tree | 830f0d9bd7b448c72d1e7e656d2f01df9090545f /dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt | |
| parent | 2da0a124188c06222ce729401733644e246c2a16 (diff) | |
| download | barebox-419db1f984f94aaa657f6c2c976afa8fcaecc42d.tar.gz barebox-419db1f984f94aaa657f6c2c976afa8fcaecc42d.tar.xz | |
dts: update to v5.3-rc7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt')
| -rw-r--r-- | dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt index 09fc02b998..a5c1db95b3 100644 --- a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt +++ b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt @@ -1,20 +1,30 @@ * ARC-HS Interrupt Distribution Unit - This optional 2nd level interrupt controller can be used in SMP configurations for - dynamic IRQ routing, load balancing of common/external IRQs towards core intc. + This optional 2nd level interrupt controller can be used in SMP configurations + for dynamic IRQ routing, load balancing of common/external IRQs towards core + intc. Properties: - compatible: "snps,archs-idu-intc" - interrupt-controller: This is an interrupt controller. -- #interrupt-cells: Must be <1>. - - Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N - of the particular interrupt line of IDU corresponds to the line N+24 of the - core interrupt controller. - - intc accessed via the special ARC AUX register interface, hence "reg" property - is not specified. +- #interrupt-cells: Must be <1> or <2>. + + Value of the first cell specifies the "common" IRQ from peripheral to IDU. + Number N of the particular interrupt line of IDU corresponds to the line N+24 + of the core interrupt controller. + + The (optional) second cell specifies any of the following flags: + - bits[3:0] trigger type and level flags + 1 = low-to-high edge triggered + 2 = NOT SUPPORTED (high-to-low edge triggered) + 4 = active high level-sensitive <<< DEFAULT + 8 = NOT SUPPORTED (active low level-sensitive) + When no second cell is specified, the interrupt is assumed to be level + sensitive. + + The interrupt controller is accessed via the special ARC AUX register + interface, hence "reg" property is not specified. Example: core_intc: core-interrupt-controller { |