summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/interrupt-controller
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2020-08-17 08:16:38 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-08-17 09:51:44 +0200
commit0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb (patch)
tree21cddf4b49891b7df21cbe5e5dd358d4e44e031d /dts/Bindings/interrupt-controller
parent8ef08db9ad225acbf7326493cc586bb14fd917f5 (diff)
downloadbarebox-0c2e2b7d8fd795c24abc7bfd3752eb3e366155eb.tar.gz
dts: update to v5.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/brcm,l2-intc.txt5
-rw-r--r--dts/Bindings/interrupt-controller/ingenic,intc.yaml22
-rw-r--r--dts/Bindings/interrupt-controller/loongson,htvec.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/loongson,liointc.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/mips-gic.txt67
-rw-r--r--dts/Bindings/interrupt-controller/mrvl,intc.txt64
-rw-r--r--dts/Bindings/interrupt-controller/mrvl,intc.yaml134
-rw-r--r--dts/Bindings/interrupt-controller/mti,gic.yaml146
-rw-r--r--dts/Bindings/interrupt-controller/renesas,rza1-irqc.txt43
-rw-r--r--dts/Bindings/interrupt-controller/renesas,rza1-irqc.yaml80
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-intr.txt2
12 files changed, 382 insertions, 193 deletions
diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml
index 96f8803..0688996 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic.yaml
@@ -42,8 +42,8 @@ properties:
- items:
- const: arm,gic-400
- enum:
- - arm,cortex-a15-gic
- - arm,cortex-a7-gic
+ - arm,cortex-a15-gic
+ - arm,cortex-a7-gic
- items:
- const: arm,arm1176jzf-devchip-gic
diff --git a/dts/Bindings/interrupt-controller/brcm,l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
index d514ec0..021cf82 100644
--- a/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
@@ -2,7 +2,10 @@ Broadcom Generic Level 2 Interrupt Controller
Required properties:
-- compatible: should be "brcm,l2-intc" for latched interrupt controllers
+- compatible: should be one of:
+ "brcm,hif-spi-l2-intc" or
+ "brcm,upg-aux-aon-l2-intc" or
+ "brcm,l2-intc" for latched interrupt controllers
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
diff --git a/dts/Bindings/interrupt-controller/ingenic,intc.yaml b/dts/Bindings/interrupt-controller/ingenic,intc.yaml
index 28b27e1..02a3cf4 100644
--- a/dts/Bindings/interrupt-controller/ingenic,intc.yaml
+++ b/dts/Bindings/interrupt-controller/ingenic,intc.yaml
@@ -16,20 +16,20 @@ properties:
compatible:
oneOf:
- enum:
- - ingenic,jz4740-intc
- - ingenic,jz4760-intc
- - ingenic,jz4780-intc
+ - ingenic,jz4740-intc
+ - ingenic,jz4760-intc
+ - ingenic,jz4780-intc
- items:
- - enum:
- - ingenic,jz4775-intc
- - ingenic,jz4770-intc
- - const: ingenic,jz4760-intc
+ - enum:
+ - ingenic,jz4775-intc
+ - ingenic,jz4770-intc
+ - const: ingenic,jz4760-intc
- items:
- - const: ingenic,x1000-intc
- - const: ingenic,jz4780-intc
+ - const: ingenic,x1000-intc
+ - const: ingenic,jz4780-intc
- items:
- - const: ingenic,jz4725b-intc
- - const: ingenic,jz4740-intc
+ - const: ingenic,jz4725b-intc
+ - const: ingenic,jz4740-intc
"#interrupt-cells":
const: 1
diff --git a/dts/Bindings/interrupt-controller/loongson,htvec.yaml b/dts/Bindings/interrupt-controller/loongson,htvec.yaml
index e865cd8..87a7455 100644
--- a/dts/Bindings/interrupt-controller/loongson,htvec.yaml
+++ b/dts/Bindings/interrupt-controller/loongson,htvec.yaml
@@ -22,8 +22,8 @@ properties:
interrupts:
minItems: 1
- maxItems: 4
- description: Four parent interrupts that receive chained interrupts.
+ maxItems: 8
+ description: Eight parent interrupts that receive chained interrupts.
interrupt-controller: true
diff --git a/dts/Bindings/interrupt-controller/loongson,liointc.yaml b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
index b1db21e..03fc4f5 100644
--- a/dts/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -51,8 +51,8 @@ properties:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
- and each bit in the cell refers to a children interrupt fron 0 to 31.
- If a CPU interrupt line didn't connected with liointc, then keep it's
+ and each bit in the cell refers to a child interrupt from 0 to 31.
+ If a CPU interrupt line didn't connect with liointc, then keep its
cell with zero.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
diff --git a/dts/Bindings/interrupt-controller/mips-gic.txt b/dts/Bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 1735953..0000000
--- a/dts/Bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs. The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt specifier. Should be 3.
- - The first cell is the type of interrupt, local or shared.
- See <include/dt-bindings/interrupt-controller/mips-gic.h>.
- - The second cell is the GIC interrupt number.
- - The third cell encodes the interrupt flags.
- See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
- flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers. If not present,
- the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
- to which the GIC may not route interrupts. Valid values are 2 - 7.
- This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
- reserved for IPIs.
- It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
- of the reserved range.
- If not specified, the driver will allocate the last 2 * number of VPEs in the
- system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
- gic: interrupt-controller@1bdc0000 {
- compatible = "mti,gic";
- reg = <0x1bdc0000 0x20000>;
-
- interrupt-controller;
- #interrupt-cells = <3>;
-
- mti,reserved-cpu-vectors = <7>;
- mti,reserved-ipi-vectors = <40 8>;
-
- timer {
- compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clock-frequency = <50000000>;
- };
- };
-
- uart@18101400 {
- ...
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
- ...
- };
diff --git a/dts/Bindings/interrupt-controller/mrvl,intc.txt b/dts/Bindings/interrupt-controller/mrvl,intc.txt
deleted file mode 100644
index a0ed027..0000000
--- a/dts/Bindings/interrupt-controller/mrvl,intc.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-* Marvell MMP Interrupt controller
-
-Required properties:
-- compatible : Should be
- "mrvl,mmp-intc" on Marvel MMP,
- "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
- "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
-- reg : Address and length of the register set of the interrupt controller.
- If the interrupt controller is intc, address and length means the range
- of the whole interrupt controller. The "marvell,mmp3-intc" controller
- also has a secondary range for the second CPU core. If the interrupt
- controller is mux-intc, address and length means one register. Since
- address of mux-intc is in the range of intc. mux-intc is secondary
- interrupt controller.
-- reg-names : Name of the register set of the interrupt controller. It's
- only required in mux-intc interrupt controller.
-- interrupts : Should be the port interrupt shared by mux interrupts. It's
- only required in mux-intc interrupt controller.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source.
-- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
- controller.
-- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
- detection first.
-
-Example:
- intc: interrupt-controller@d4282000 {
- compatible = "mrvl,mmp2-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xd4282000 0x1000>;
- mrvl,intc-nr-irqs = <64>;
- };
-
- intcmux4@d4282150 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x150 0x4>, <0x168 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- };
-
-* Marvell Orion Interrupt controller
-
-Required properties
-- compatible : Should be "marvell,orion-intc".
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. Supported value is <1>.
-- interrupt-controller : Declare this node to be an interrupt controller.
-- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
- One entry in the list represents 32 interrupts.
-
-Example:
-
- intc: interrupt-controller {
- compatible = "marvell,orion-intc", "marvell,intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xfed20204 0x04>,
- <0xfed20214 0x04>;
- };
diff --git a/dts/Bindings/interrupt-controller/mrvl,intc.yaml b/dts/Bindings/interrupt-controller/mrvl,intc.yaml
new file mode 100644
index 0000000..372ccbf
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mrvl,intc.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP/Orion Interrupt controller bindings
+
+maintainers:
+ - Thomas Gleixner <tglx@linutronix.de>
+ - Jason Cooper <jason@lakedaemon.net>
+ - Marc Zyngier <maz@kernel.org>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: marvell,orion-intc
+ then:
+ required:
+ - mrvl,intc-nr-irqs
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,mmp3-intc
+ - mrvl,mmp2-mux-intc
+ then:
+ properties:
+ reg:
+ minItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mrvl,mmp2-mux-intc
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: 'mux status'
+ - const: 'mux mask'
+ required:
+ - interrupts
+ else:
+ properties:
+ interrupts: false
+
+properties:
+ '#interrupt-cells':
+ const: 1
+
+ compatible:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ - marvell,mmp3-intc
+ - marvell,orion-intc
+ - mrvl,mmp2-mux-intc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names: true
+
+ interrupts: true
+
+ interrupt-controller: true
+
+ mrvl,intc-nr-irqs:
+ description: |
+ Specifies the number of interrupts in the interrupt controller.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ mrvl,clr-mfp-irq:
+ description: |
+ Specifies the interrupt that needs to clear MFP edge detection first.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@d4282000 {
+ compatible = "mrvl,mmp2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xd4282000 0x1000>;
+ mrvl,intc-nr-irqs = <64>;
+ };
+
+ interrupt-controller@d4282150 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x150 0x4>, <0x168 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+ - |
+ interrupt-controller@fed20204 {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xfed20204 0x04>,
+ <0xfed20214 0x04>;
+ };
+
+...
diff --git a/dts/Bindings/interrupt-controller/mti,gic.yaml b/dts/Bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 0000000..ce6aaff
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+ - Paul Burton <paulburton@kernel.org>
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+ The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+ It also supports local (per-processor) interrupts and software-generated
+ interrupts which can be used as IPIs. The GIC also includes a free-running
+ global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+ compatible:
+ const: mti,gic
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ The 1st cell is the type of interrupt: local or shared defined in the
+ file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+ GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+ the IRQ trigger modes, which are defined in the file
+ 'dt-bindings/interrupt-controller/irq.h'.
+
+ reg:
+ description: |
+ Base address and length of the GIC registers space. If not present,
+ the base address reported by the hardware GCR_GIC_BASE will be used.
+ maxItems: 1
+
+ interrupt-controller: true
+
+ mti,reserved-cpu-vectors:
+ description: |
+ Specifies the list of CPU interrupt vectors to which the GIC may not
+ route interrupts. This property is ignored if the CPU is started in EIC
+ mode.
+ $ref: /schemas/types.yaml#definitions/uint32-array
+ minItems: 1
+ maxItems: 6
+ uniqueItems: true
+ items:
+ minimum: 2
+ maximum: 7
+
+ mti,reserved-ipi-vectors:
+ description: |
+ Specifies the range of GIC interrupts that are reserved for IPIs.
+ It accepts two values: the 1st is the starting interrupt and the 2nd is
+ the size of the reserved range. If not specified, the driver will
+ allocate the last (2 * number of VPEs in the system).
+ $ref: /schemas/types.yaml#definitions/uint32-array
+ items:
+ - minimum: 0
+ maximum: 254
+ - minimum: 2
+ maximum: 254
+
+ timer:
+ type: object
+ description: |
+ MIPS GIC includes a free-running global timer, per-CPU count/compare
+ timers, and a watchdog. Currently only the GIC Timer is supported.
+ properties:
+ compatible:
+ const: mti,gic-timer
+
+ interrupts:
+ description: |
+ Interrupt for the GIC local timer, so normally it's suppose to be of
+ <GIC_LOCAL X IRQ_TYPE_NONE> format.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency: true
+
+ required:
+ - compatible
+ - interrupts
+
+ oneOf:
+ - required:
+ - clocks
+ - required:
+ - clock-frequency
+
+ additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - "#interrupt-cells"
+ - interrupt-controller
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ mti,reserved-cpu-vectors = <7>;
+ mti,reserved-ipi-vectors = <40 8>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clock-frequency = <50000000>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&cpu_pll>;
+ };
+ };
+ - |
+ interrupt-controller {
+ compatible = "mti,gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+...
diff --git a/dts/Bindings/interrupt-controller/renesas,rza1-irqc.txt b/dts/Bindings/interrupt-controller/renesas,rza1-irqc.txt
deleted file mode 100644
index 727b7e4..0000000
--- a/dts/Bindings/interrupt-controller/renesas,rza1-irqc.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-DT bindings for the Renesas RZ/A1 Interrupt Controller
-
-The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
-RZ/A1 and RZ/A2 SoCs:
- - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
- interrupts,
- - NMI edge select.
-
-Required properties:
- - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
- fallback.
- Examples with soctypes are:
- - "renesas,r7s72100-irqc" (RZ/A1H)
- - "renesas,r7s9210-irqc" (RZ/A2M)
- - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
- in interrupts.txt in this directory)
- - #address-cells: Must be zero
- - interrupt-controller: Marks the device as an interrupt controller
- - reg: Base address and length of the memory resource used by the interrupt
- controller
- - interrupt-map: Specifies the mapping from external interrupts to GIC
- interrupts
- - interrupt-map-mask: Must be <7 0>
-
-Example:
-
- irqc: interrupt-controller@fcfef800 {
- compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
- #interrupt-cells = <2>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0xfcfef800 0x6>;
- interrupt-map =
- <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-map-mask = <7 0>;
- };
diff --git a/dts/Bindings/interrupt-controller/renesas,rza1-irqc.yaml b/dts/Bindings/interrupt-controller/renesas,rza1-irqc.yaml
new file mode 100644
index 0000000..755cdfa
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/renesas,rza1-irqc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/A1 Interrupt Controller
+
+maintainers:
+ - Chris Brandt <chris.brandt@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+ The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
+ RZ/A2 SoCs:
+ - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
+ - NMI edge select.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r7s72100-irqc # RZ/A1H
+ - renesas,r7s9210-irqc # RZ/A2M
+ - const: renesas,rza1-irqc
+
+ '#interrupt-cells':
+ const: 2
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupt-map:
+ maxItems: 8
+ description: Specifies the mapping from external interrupts to GIC interrupts.
+
+ interrupt-map-mask:
+ items:
+ - const: 7
+ - const: 0
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+ - interrupt-map
+ - interrupt-map-mask
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
diff --git a/dts/Bindings/interrupt-controller/ti,sci-intr.txt b/dts/Bindings/interrupt-controller/ti,sci-intr.txt
index 1a8718f..178fca0 100644
--- a/dts/Bindings/interrupt-controller/ti,sci-intr.txt
+++ b/dts/Bindings/interrupt-controller/ti,sci-intr.txt
@@ -55,7 +55,7 @@ Required Properties:
corresponds to a range of host irqs.
For more details on TISCI IRQ resource management refer:
-http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
+https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
Example:
--------