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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:34:01 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:40 +0100 |
commit | 24693d83ce52959f227b11af2e040473dba55221 (patch) | |
tree | 97720d915d50fc8b32326409def3a79e2a0bf907 /dts/Bindings/interrupt-controller | |
parent | 940968e2208b97d74e18b082500f35e463bcece5 (diff) | |
download | barebox-24693d83ce52959f227b11af2e040473dba55221.tar.gz barebox-24693d83ce52959f227b11af2e040473dba55221.tar.xz |
dts: update to v4.3-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r-- | dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt index 391717a68f..ec96b1f014 100644 --- a/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt +++ b/dts/Bindings/interrupt-controller/qca,ath79-misc-intc.txt @@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority interrupt. Required Properties: -- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" - as fallback +- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or + "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" - reg: Base address and size of the controllers memory area - interrupt-parent: phandle of the parent interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. @@ -13,6 +13,9 @@ Required Properties: - #interrupt-cells : Specifies the number of cells needed to encode interrupt source, should be 1 +Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, +use ar7240 for all other SoCs. + Please refer to interrupts.txt in this directory for details of the common Interrupt Controllers bindings used by client devices. @@ -28,3 +31,16 @@ Example: interrupt-controller; #interrupt-cells = <1>; }; + +Another example: + + interrupt-controller@18060010 { + compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; |