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authorSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-11-17 07:36:09 +0100
commit3f2f5980d517b6a71ffe54e615bd3a4b58b1c295 (patch)
treeeb5a7bfce811d20e58dd0eb1add0f6cf0e6b86e0 /dts/Bindings/interrupt-controller
parent81ceab95360295cef146e89a1cd1cd5e590aa75e (diff)
downloadbarebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.gz
barebox-3f2f5980d517b6a71ffe54e615bd3a4b58b1c295.tar.xz
dts: update to v5.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/microchip,eic.yaml73
-rw-r--r--dts/Bindings/interrupt-controller/msi-controller.yaml46
-rw-r--r--dts/Bindings/interrupt-controller/renesas,irqc.yaml1
-rw-r--r--dts/Bindings/interrupt-controller/st,stm32-exti.yaml4
4 files changed, 122 insertions, 2 deletions
diff --git a/dts/Bindings/interrupt-controller/microchip,eic.yaml b/dts/Bindings/interrupt-controller/microchip,eic.yaml
new file mode 100644
index 0000000000..50003880ee
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/microchip,eic.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip External Interrupt Controller
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+description:
+ This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
+ support for handling up to 2 external interrupt lines.
+
+properties:
+ compatible:
+ enum:
+ - microchip,sama7g5-eic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description:
+ The first cell is the input IRQ number (between 0 and 1), the second cell
+ is the trigger type as defined in interrupt.txt present in this directory.
+
+ interrupts:
+ description: |
+ Contains the GIC SPI IRQs mapped to the external interrupt lines. They
+ should be specified sequentially from output 0 to output 1.
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: pclk
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ eic: interrupt-controller@e1628000 {
+ compatible = "microchip,sama7g5-eic";
+ reg = <0xe1628000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
+ clock-names = "pclk";
+ };
+
+...
diff --git a/dts/Bindings/interrupt-controller/msi-controller.yaml b/dts/Bindings/interrupt-controller/msi-controller.yaml
new file mode 100644
index 0000000000..449d6067ec
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/msi-controller.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSI controller
+
+maintainers:
+ - Marc Zyngier <maz@kernel.org>
+
+description: |
+ An MSI controller signals interrupts to a CPU when a write is made
+ to an MMIO address by some master. An MSI controller may feature a
+ number of doorbells.
+
+properties:
+ "#msi-cells":
+ description: |
+ The number of cells in an msi-specifier, required if not zero.
+
+ Typically this will encode information related to sideband data,
+ and will not encode doorbells or payloads as these can be
+ configured dynamically.
+
+ The meaning of the msi-specifier is defined by the device tree
+ binding of the specific MSI controller.
+ enum: [0, 1]
+
+ msi-controller:
+ description:
+ Identifies the node as an MSI controller.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ msi-ranges:
+ description:
+ A list of <phandle intspec span> tuples, where "phandle" is the
+ parent interrupt controller, "intspec" is the starting/base
+ interrupt specifier and "span" is the size of the
+ range. Multiple ranges can be provided.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+dependencies:
+ "#msi-cells": [ msi-controller ]
+
+additionalProperties: true
diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.yaml b/dts/Bindings/interrupt-controller/renesas,irqc.yaml
index abb22db3bb..79d0358e2f 100644
--- a/dts/Bindings/interrupt-controller/renesas,irqc.yaml
+++ b/dts/Bindings/interrupt-controller/renesas,irqc.yaml
@@ -27,6 +27,7 @@ properties:
- renesas,intc-ex-r8a774a1 # RZ/G2M
- renesas,intc-ex-r8a774b1 # RZ/G2N
- renesas,intc-ex-r8a774c0 # RZ/G2E
+ - renesas,intc-ex-r8a774e1 # RZ/G2H
- renesas,intc-ex-r8a7795 # R-Car H3
- renesas,intc-ex-r8a7796 # R-Car M3-W
- renesas,intc-ex-r8a77961 # R-Car M3-W+
diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
index 6d3e68eb2e..d19c881b4a 100644
--- a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
+++ b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: STM32 External Interrupt Controller Device Tree Bindings
maintainers:
- - Alexandre Torgue <alexandre.torgue@st.com>
- - Ludovic Barre <ludovic.barre@st.com>
+ - Alexandre Torgue <alexandre.torgue@foss.st.com>
+ - Ludovic Barre <ludovic.barre@foss.st.com>
properties:
compatible: