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authorSascha Hauer <s.hauer@pengutronix.de>2020-04-20 15:07:38 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-04-27 21:17:17 +0200
commit8d158e1a40917e48cb68131a6cfd1b8755a4d8a0 (patch)
tree76118ca8fbf736bbdbc30b9fa2480a0d2a775597 /dts/Bindings/interrupt-controller
parent15d46bac2280def447c7fd74686d44d938c24556 (diff)
downloadbarebox-8d158e1a40917e48cb68131a6cfd1b8755a4d8a0.tar.gz
dts: update to v5.7-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/loongson,htpic.yaml59
-rw-r--r--dts/Bindings/interrupt-controller/loongson,liointc.yaml93
-rw-r--r--dts/Bindings/interrupt-controller/msi.txt2
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--dts/Bindings/interrupt-controller/socionext,uniphier-aidet.yaml61
6 files changed, 216 insertions, 33 deletions
diff --git a/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
index 507c141..ccc507f 100644
--- a/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
+++ b/dts/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
@@ -44,6 +44,8 @@ required:
- interrupt-controller
- '#interrupt-cells'
+additionalProperties: false
+
examples:
- |
intcon: interrupt-controller@c8003000 {
diff --git a/dts/Bindings/interrupt-controller/loongson,htpic.yaml b/dts/Bindings/interrupt-controller/loongson,htpic.yaml
new file mode 100644
index 0000000..c8861cb
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/loongson,htpic.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson-3 HyperTransport Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips to transmit
+ interrupts from PCH PIC connected on HyperTransport bus.
+
+properties:
+ compatible:
+ const: loongson,htpic-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Four parent interrupts that receive chained interrupts.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ htintc: interrupt-controller@1fb000080 {
+ compatible = "loongson,htintc-1.0";
+ reg = <0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
diff --git a/dts/Bindings/interrupt-controller/loongson,liointc.yaml b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
new file mode 100644
index 0000000..9c6b91f
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson Local I/O Interrupt Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |
+ This interrupt controller is found in the Loongson-3 family of chips as the primary
+ package interrupt controller which can route local I/O interrupt to interrupt lines
+ of cores.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,liointc-1.0
+ - const: loongson,liointc-1.0a
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ description:
+ Interrupt source of the CPU interrupts.
+ minItems: 1
+ maxItems: 4
+
+ interrupt-names:
+ description: List of names for the parent interrupts.
+ items:
+ - const: int0
+ - const: int1
+ - const: int2
+ - const: int3
+ minItems: 1
+ maxItems: 4
+
+ '#interrupt-cells':
+ const: 2
+
+ 'loongson,parent_int_map':
+ description: |
+ This property points how the children interrupts will be mapped into CPU
+ interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
+ and each bit in the cell refers to a children interrupt fron 0 to 31.
+ If a CPU interrupt line didn't connected with liointc, then keep it's
+ cell with zero.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - items:
+ minItems: 4
+ maxItems: 4
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - 'loongson,parent_int_map'
+
+
+examples:
+ - |
+ iointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+...
diff --git a/dts/Bindings/interrupt-controller/msi.txt b/dts/Bindings/interrupt-controller/msi.txt
index c60c034..c20b51d 100644
--- a/dts/Bindings/interrupt-controller/msi.txt
+++ b/dts/Bindings/interrupt-controller/msi.txt
@@ -98,7 +98,7 @@ Example
};
msi_c: msi-controller@c {
- reg = <0xb 0xf00>;
+ reg = <0xc 0xf00>;
compatible = "vendor-b,another-controller";
msi-controller;
/* Each device has some unique ID */
diff --git a/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
deleted file mode 100644
index 48e71d3..0000000
--- a/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-UniPhier AIDET
-
-UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
-Interrupt Controller). GIC itself can handle only high level and rising edge
-interrupts. The AIDET provides logic inverter to support low level and falling
-edge interrupts.
-
-Required properties:
-- compatible: Should be one of the following:
- "socionext,uniphier-ld4-aidet" - for LD4 SoC
- "socionext,uniphier-pro4-aidet" - for Pro4 SoC
- "socionext,uniphier-sld8-aidet" - for sLD8 SoC
- "socionext,uniphier-pro5-aidet" - for Pro5 SoC
- "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC
- "socionext,uniphier-ld11-aidet" - for LD11 SoC
- "socionext,uniphier-ld20-aidet" - for LD20 SoC
- "socionext,uniphier-pxs3-aidet" - for PXs3 SoC
-- reg: Specifies offset and length of the register set for the device.
-- interrupt-controller: Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an interrupt
- source. The value should be 2. The first cell defines the interrupt number
- (corresponds to the SPI interrupt number of GIC). The second cell specifies
- the trigger type as defined in interrupts.txt in this directory.
-
-Example:
-
- aidet: aidet@5fc20000 {
- compatible = "socionext,uniphier-pro4-aidet";
- reg = <0x5fc20000 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.yaml
new file mode 100644
index 0000000..f89ebde
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/socionext,uniphier-aidet.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier AIDET
+
+description: |
+ UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
+ (Generic Interrupt Controller). GIC itself can handle only high level and
+ rising edge interrupts. The AIDET provides logic inverter to support low
+ level and falling edge interrupts.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-ld4-aidet
+ - socionext,uniphier-pro4-aidet
+ - socionext,uniphier-sld8-aidet
+ - socionext,uniphier-pro5-aidet
+ - socionext,uniphier-pxs2-aidet
+ - socionext,uniphier-ld6b-aidet
+ - socionext,uniphier-ld11-aidet
+ - socionext,uniphier-ld20-aidet
+ - socionext,uniphier-pxs3-aidet
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description: |
+ The first cell defines the interrupt number (corresponds to the SPI
+ interrupt number of GIC). The second cell specifies the trigger type as
+ defined in interrupts.txt in this directory.
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };