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authorSascha Hauer <s.hauer@pengutronix.de>2014-06-17 22:16:07 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2014-06-19 09:41:51 +0200
commit9313920df6d3d55fbd03ce8ec1c0da9a10c29824 (patch)
treeef80d80abbaf46293b777ead52caddd9d5d97644 /dts/Bindings/interrupt-controller
parent83e875e1f45beffe399cff0ff6128e0fca9da168 (diff)
downloadbarebox-9313920df6d3d55fbd03ce8ec1c0da9a10c29824.tar.gz
dts: update to v3.16-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/brcm,l2-intc.txt29
-rw-r--r--dts/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt38
2 files changed, 67 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/brcm,l2-intc.txt b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
new file mode 100644
index 0000000..448273a
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/brcm,l2-intc.txt
@@ -0,0 +1,29 @@
+Broadcom Generic Level 2 Interrupt Controller
+
+Required properties:
+
+- compatible: should be "brcm,l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an
+ interrupt source. Should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+ this controller is cacaded from
+- interrupts: specifies the interrupt line in the interrupt-parent irq space
+ to be used for cascading
+
+Optional properties:
+
+- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
+ wakeup source for system suspend/resume.
+
+Example:
+
+hif_intr2_intc: interrupt-controller@f0441000 {
+ compatible = "brcm,l2-intc";
+ reg = <0xf0441000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <0x0 0x20 0x0>;
+};
diff --git a/dts/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/dts/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
new file mode 100644
index 0000000..5fc0313
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
@@ -0,0 +1,38 @@
+Marvell Armada 370, 375, 38x, XP Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible: Should be "marvell,mpic"
+- interrupt-controller: Identifies the node as an interrupt controller.
+- msi-controller: Identifies the node as an PCI Message Signaled
+ Interrupt controller.
+- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
+ The cell is the IRQ number
+
+- reg: Should contain PMIC registers location and length. First pair
+ for the main interrupt registers, second pair for the per-CPU
+ interrupt registers. For this last pair, to be compliant with SMP
+ support, the "virtual" must be use (For the record, these registers
+ automatically map to the interrupt controller registers of the
+ current CPU)
+
+Optional properties:
+
+- interrupts: If defined, then it indicates that this MPIC is
+ connected as a slave to another interrupt controller. This is
+ typically the case on Armada 375 and Armada 38x, where the MPIC is
+ connected as a slave to the Cortex-A9 GIC. The provided interrupt
+ indicate to which GIC interrupt the MPIC output is connected.
+
+Example:
+
+ mpic: interrupt-controller@d0020000 {
+ compatible = "marvell,mpic";
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ msi-controller;
+ reg = <0xd0020a00 0x1d0>,
+ <0xd0021070 0x58>;
+ };