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authorSascha Hauer <s.hauer@pengutronix.de>2017-02-10 08:51:35 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-02-10 08:51:35 +0100
commitcbf19c96efb552603541279a467ff577faaba995 (patch)
tree6442400a0005d898425be95601b4b015bdd318a7 /dts/Bindings/interrupt-controller
parentf4db58d47c68b28dd509ceca39e1aa749c61f828 (diff)
downloadbarebox-cbf19c96efb552603541279a467ff577faaba995.tar.gz
dts: update to v4.10-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
index 0dcb7c7..9446576 100644
--- a/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/dts/Bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -15,6 +15,9 @@ Properties:
Second cell specifies the irq distribution mode to cores
0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
+ The second cell in interrupts property is deprecated and may be ignored by
+ the kernel.
+
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.