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authorLucas Stach <l.stach@pengutronix.de>2017-07-31 20:03:05 +0200
committerLucas Stach <l.stach@pengutronix.de>2017-07-31 20:03:05 +0200
commitd14b844b08635c717fb52a294ed8d6872e260315 (patch)
tree18607dcdd29688b2fa9528f79423183a68e9898d /dts/Bindings/interrupt-controller
parent858b797e529e26c19bfa893fdb37ed67ff7a6006 (diff)
downloadbarebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.gz
dts: update to v4.13-rc2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt7
-rw-r--r--dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt25
-rw-r--r--dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt9
-rw-r--r--dts/Bindings/interrupt-controller/marvell,gicp.txt27
-rw-r--r--dts/Bindings/interrupt-controller/marvell,icu.txt51
-rw-r--r--dts/Bindings/interrupt-controller/mediatek,sysirq.txt28
-rw-r--r--dts/Bindings/interrupt-controller/open-pic.txt5
7 files changed, 130 insertions, 22 deletions
diff --git a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 81cd369..4ae553e 100644
--- a/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/dts/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
Required properties:
-- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
- "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
+- compatible : should be one of the following:
+ - "allwinner,sun7i-a20-sc-nmi"
+ - "allwinner,sun6i-a31-sc-nmi" (deprecated)
+ - "allwinner,sun6i-a31-r-intc"
+ - "allwinner,sun9i-a80-nmi"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
new file mode 100644
index 0000000..033cc82
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt
@@ -0,0 +1,25 @@
+Device tree configuration for the I2C Interrupt Controller on the AST24XX and
+AST25XX SoCs.
+
+Required Properties:
+- #address-cells : should be 1
+- #size-cells : should be 1
+- #interrupt-cells : should be 1
+- compatible : should be "aspeed,ast2400-i2c-ic"
+ or "aspeed,ast2500-i2c-ic"
+- reg : address start and range of controller
+- interrupts : interrupt number
+- interrupt-controller : denotes that the controller receives and fires
+ new interrupts for child busses
+
+Example:
+
+i2c_ic: interrupt-controller@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2400-i2c-ic";
+ reg = <0x0 0x40>;
+ interrupts = <12>;
+ interrupt-controller;
+};
diff --git a/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
index 6c6e853..e3fea07 100644
--- a/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
+++ b/dts/Bindings/interrupt-controller/aspeed,ast2400-vic.txt
@@ -1,12 +1,13 @@
Aspeed Vectored Interrupt Controller
-These bindings are for the Aspeed AST2400 interrupt controller register layout.
-The SoC has an legacy register layout, but this driver does not support that
-mode of operation.
+These bindings are for the Aspeed interrupt controller. The AST2400 and
+AST2500 SoC families include a legacy register layout before a re-designed
+layout, but the bindings do not prescribe the use of one or the other.
Required properties:
-- compatible : should be "aspeed,ast2400-vic".
+- compatible : "aspeed,ast2400-vic"
+ "aspeed,ast2500-vic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
diff --git a/dts/Bindings/interrupt-controller/marvell,gicp.txt b/dts/Bindings/interrupt-controller/marvell,gicp.txt
new file mode 100644
index 0000000..64a00ce
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,gicp.txt
@@ -0,0 +1,27 @@
+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,ap806-gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
+ for this GICP
+
+- msi-controller: indicates that this is an MSI controller
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+};
diff --git a/dts/Bindings/interrupt-controller/marvell,icu.txt b/dts/Bindings/interrupt-controller/marvell,icu.txt
new file mode 100644
index 0000000..aa8bf2e
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/marvell,icu.txt
@@ -0,0 +1,51 @@
+Marvell ICU Interrupt Controller
+--------------------------------
+
+The Marvell ICU (Interrupt Consolidation Unit) controller is
+responsible for collecting all wired-interrupt sources in the CP and
+communicating them to the GIC in the AP, the unit translates interrupt
+requests on input wires to MSG memory mapped transactions to the GIC.
+
+Required properties:
+
+- compatible: Should be "marvell,cp110-icu"
+
+- reg: Should contain ICU registers location and length.
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 3.
+
+ The 1st cell is the group type of the ICU interrupt. Possible group
+ types are:
+
+ ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
+ ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
+ ICU_GRP_SEI (0x4) : System error interrupt
+ ICU_GRP_REI (0x5) : RAM error interrupt
+
+ The 2nd cell is the index of the interrupt in the ICU unit.
+
+ The 3rd cell is the type of the interrupt. See arm,gic.txt for
+ details.
+
+- interrupt-controller: Identifies the node as an interrupt
+ controller.
+
+- msi-parent: Should point to the GICP controller, the GIC extension
+ that allows to trigger interrupts using MSG memory mapped
+ transactions.
+
+Example:
+
+icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+};
+
+usb3h0: usb3@500000 {
+ interrupt-parent = <&icu>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..11cc87a 100644
--- a/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/dts/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,21 +1,23 @@
-+Mediatek 65xx/67xx/81xx sysirq
++Mediatek MT65xx/MT67xx/MT81xx sysirq
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
-- compatible: should be one of:
- "mediatek,mt8173-sysirq"
- "mediatek,mt8135-sysirq"
- "mediatek,mt8127-sysirq"
- "mediatek,mt6795-sysirq"
- "mediatek,mt6755-sysirq"
- "mediatek,mt6592-sysirq"
- "mediatek,mt6589-sysirq"
- "mediatek,mt6582-sysirq"
- "mediatek,mt6580-sysirq"
- "mediatek,mt6577-sysirq"
- "mediatek,mt2701-sysirq"
+- compatible: should be
+ "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
+ "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
+ "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
+ "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
+ "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
+ "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
+ "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
+ "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
+ "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
+ "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
+ "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
+ "mediatek,mt6577-sysirq": for MT6577
+ "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/dts/Bindings/interrupt-controller/open-pic.txt b/dts/Bindings/interrupt-controller/open-pic.txt
index 909a902..ccbbfdc 100644
--- a/dts/Bindings/interrupt-controller/open-pic.txt
+++ b/dts/Bindings/interrupt-controller/open-pic.txt
@@ -92,7 +92,6 @@ Example 2:
* References
-[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
- Requirements (ePAPR), Version 1.0, July 2008.
- (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)
+[1] Devicetree Specification
+ (https://www.devicetree.org/specifications/)