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authorSascha Hauer <s.hauer@pengutronix.de>2018-06-21 13:44:30 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-06-22 08:16:13 +0200
commite4067b75fb6ca83a58b2c342a0b3ee12e1223c4e (patch)
treebe013bf46292f4696ac776bc91c1cf35b7adab24 /dts/Bindings/interrupt-controller
parentfe040e0977fab29216f5039e8f9b04e6dbec859a (diff)
downloadbarebox-e4067b75fb6ca83a58b2c342a0b3ee12e1223c4e.tar.gz
dts: update to v4.18-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/interrupt-controller')
-rw-r--r--dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt11
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic-v3.txt17
-rw-r--r--dts/Bindings/interrupt-controller/st,stm32-exti.txt3
3 files changed, 26 insertions, 5 deletions
diff --git a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index a83f9a5..89674ad 100644
--- a/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/dts/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -9,11 +9,12 @@ number of interrupt exposed depends on the SoC.
Required properties:
-- compatible : must have "amlogic,meson8-gpio-intc” and either
- “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
- “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
- “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
- “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
+- compatible : must have "amlogic,meson8-gpio-intc" and either
+ "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
+ "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
+ "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
+ "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
+ "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
- interrupt-parent : a phandle to the GIC the interrupts are routed to.
Usually this is provided at the root level of the device tree as it is
common to most of the SoC.
diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.txt b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
index 0a57f2f..3ea78c4 100644
--- a/dts/Bindings/interrupt-controller/arm,gic-v3.txt
+++ b/dts/Bindings/interrupt-controller/arm,gic-v3.txt
@@ -57,6 +57,20 @@ Optional
occupied by the redistributors. Required if more than one such
region is present.
+- msi-controller: Boolean property. Identifies the node as an MSI
+ controller. Only present if the Message Based Interrupt
+ functionnality is being exposed by the HW, and the mbi-ranges
+ property present.
+
+- mbi-ranges: A list of pairs <intid span>, where "intid" is the first
+ SPI of a range that can be used an MBI, and "span" the size of that
+ range. Multiple ranges can be provided. Requires "msi-controller" to
+ be set.
+
+- mbi-alias: Address property. Base address of an alias of the GICD
+ region containing only the {SET,CLR}SPI registers to be used if
+ isolation is required, and if supported by the HW.
+
Sub-nodes:
PPI affinity can be expressed as a single "ppi-partitions" node,
@@ -99,6 +113,9 @@ Examples:
<0x0 0x2c020000 0 0x2000>; // GICV
interrupts = <1 9 4>;
+ msi-controller;
+ mbi-ranges = <256 128>;
+
gic-its@2c200000 {
compatible = "arm,gic-v3-its";
msi-controller;
diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.txt b/dts/Bindings/interrupt-controller/st,stm32-exti.txt
index edf03f0..136bd61 100644
--- a/dts/Bindings/interrupt-controller/st,stm32-exti.txt
+++ b/dts/Bindings/interrupt-controller/st,stm32-exti.txt
@@ -5,11 +5,14 @@ Required properties:
- compatible: Should be:
"st,stm32-exti"
"st,stm32h7-exti"
+ "st,stm32mp1-exti"
- reg: Specifies base physical address and size of the registers
- interrupt-controller: Indentifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells to encode an interrupt
specifier, shall be 2
- interrupts: interrupts references to primary interrupt controller
+ (only needed for exti controller with multiple exti under
+ same parent interrupt: st,stm32-exti and st,stm32h7-exti")
Example: