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| author | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:03:05 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-07-31 20:03:05 +0200 |
| commit | d14b844b08635c717fb52a294ed8d6872e260315 (patch) | |
| tree | 18607dcdd29688b2fa9528f79423183a68e9898d /dts/Bindings/iommu/arm,smmu-v3.txt | |
| parent | 858b797e529e26c19bfa893fdb37ed67ff7a6006 (diff) | |
| download | barebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.gz barebox-d14b844b08635c717fb52a294ed8d6872e260315.tar.xz | |
dts: update to v4.13-rc2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'dts/Bindings/iommu/arm,smmu-v3.txt')
| -rw-r--r-- | dts/Bindings/iommu/arm,smmu-v3.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/dts/Bindings/iommu/arm,smmu-v3.txt b/dts/Bindings/iommu/arm,smmu-v3.txt index be57550e14..c9abbf3e4f 100644 --- a/dts/Bindings/iommu/arm,smmu-v3.txt +++ b/dts/Bindings/iommu/arm,smmu-v3.txt @@ -26,6 +26,12 @@ the PCIe specification. * "priq" - PRI Queue not empty * "cmdq-sync" - CMD_SYNC complete * "gerror" - Global Error activated + * "combined" - The combined interrupt is optional, + and should only be provided if the + hardware supports just a single, + combined interrupt line. + If provided, then the combined interrupt + will be used in preference to any others. - #iommu-cells : See the generic IOMMU binding described in devicetree/bindings/pci/pci-iommu.txt @@ -49,6 +55,12 @@ the PCIe specification. - hisilicon,broken-prefetch-cmd : Avoid sending CMD_PREFETCH_* commands to the SMMU. +- cavium,cn9900-broken-page1-regspace + : Replaces all page 1 offsets used for EVTQ_PROD/CONS, + PRIQ_PROD/CONS register access with page 0 offsets. + Set for Cavium ThunderX2 silicon that doesn't support + SMMU page1 register space. + ** Example smmu@2b400000 { |