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authorSascha Hauer <s.hauer@pengutronix.de>2022-06-08 09:15:32 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-06-08 10:41:39 +0200
commite54923b76e345080b73f3ae7f508657e5c63a9eb (patch)
tree8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts/Bindings/iommu/arm,smmu.yaml
parentd4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff)
downloadbarebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz
barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/iommu/arm,smmu.yaml')
-rw-r--r--dts/Bindings/iommu/arm,smmu.yaml25
1 files changed, 23 insertions, 2 deletions
diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml
index da5381c8ee..76fc2c0f4d 100644
--- a/dts/Bindings/iommu/arm,smmu.yaml
+++ b/dts/Bindings/iommu/arm,smmu.yaml
@@ -37,8 +37,10 @@ properties:
- qcom,sc7180-smmu-500
- qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
+ - qcom,sc8280xp-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
+ - qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
@@ -62,8 +64,9 @@ properties:
for improved performance.
items:
- enum:
- - nvidia,tegra194-smmu
- nvidia,tegra186-smmu
+ - nvidia,tegra194-smmu
+ - nvidia,tegra234-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
@@ -157,6 +160,17 @@ properties:
power-domains:
maxItems: 1
+ nvidia,memory-controller:
+ description: |
+ A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
+ The memory controller needs to be programmed with a mapping of memory
+ client IDs to ARM SMMU stream IDs.
+
+ If this property is absent, the mapping programmed by early firmware
+ will be used and it is not guaranteed that IOMMU translations will be
+ enabled for any given device.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
required:
- compatible
- reg
@@ -172,13 +186,20 @@ allOf:
compatible:
contains:
enum:
- - nvidia,tegra194-smmu
- nvidia,tegra186-smmu
+ - nvidia,tegra194-smmu
+ - nvidia,tegra234-smmu
then:
properties:
reg:
minItems: 1
maxItems: 2
+
+ # The reference to the memory controller is required to ensure that the
+ # memory client to stream ID mapping can be done synchronously with the
+ # IOMMU attachment.
+ required:
+ - nvidia,memory-controller
else:
properties:
reg: