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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
commit | bfbf18d991756858337f7700e8ff0a6f0dc31afc (patch) | |
tree | cf3568de4fdff1891e277507f08f49a871682706 /dts/Bindings/memory-controllers/fsl/ddr.txt | |
parent | 834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff) | |
download | barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz |
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers/fsl/ddr.txt')
-rw-r--r-- | dts/Bindings/memory-controllers/fsl/ddr.txt | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/dts/Bindings/memory-controllers/fsl/ddr.txt b/dts/Bindings/memory-controllers/fsl/ddr.txt new file mode 100644 index 0000000000..dde6d83708 --- /dev/null +++ b/dts/Bindings/memory-controllers/fsl/ddr.txt @@ -0,0 +1,29 @@ +Freescale DDR memory controller + +Properties: + +- compatible : Should include "fsl,chip-memory-controller" where + chip is the processor (bsc9132, mpc8572 etc.), or + "fsl,qoriq-memory-controller". +- reg : Address and size of DDR controller registers +- interrupts : Error interrupt of DDR controller +- little-endian : Specifies little-endian access to registers + If omitted, big-endian will be used. + +Example 1: + + memory-controller@2000 { + compatible = "fsl,bsc9132-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <16 2 1 8>; + }; + + +Example 2: + + ddr1: memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; |