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authorSascha Hauer <s.hauer@pengutronix.de>2016-02-03 10:25:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2016-02-04 08:40:36 +0100
commit0ff58575c9d66f660886387c2e68d8c5c724e87b (patch)
tree4a889d1478da83ae46db96f5c049872cdb90eeb6 /dts/Bindings/memory-controllers
parenta0da52f83c36a81984e0fca4b75d522b955df267 (diff)
downloadbarebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.gz
barebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.xz
dts: update to v4.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
-rw-r--r--dts/Bindings/memory-controllers/ath79-ddr-controller.txt8
1 files changed, 4 insertions, 4 deletions
diff --git a/dts/Bindings/memory-controllers/ath79-ddr-controller.txt b/dts/Bindings/memory-controllers/ath79-ddr-controller.txt
index efe35a065..c81af75bc 100644
--- a/dts/Bindings/memory-controllers/ath79-ddr-controller.txt
+++ b/dts/Bindings/memory-controllers/ath79-ddr-controller.txt
@@ -1,6 +1,6 @@
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
-The DDR controller of the ARxxx and AR9xxx families provides an interface
+The DDR controller of the AR7xxx and AR9xxx families provides an interface
to flush the FIFO between various devices and the DDR. This is mainly used
by the IRQ controller to flush the FIFO before running the interrupt handler
of such devices.
@@ -11,9 +11,9 @@ Required properties:
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
-- reg: Base address and size of the controllers memory area
-- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
- channel
+- reg: Base address and size of the controller's memory area
+- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
+ the write buffer channel index, should be 1.
Example: