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authorSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:47:00 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-12-19 05:47:00 +0100
commit17a537847ed3b1c0fcae46a43e1374868dc7dae6 (patch)
tree2fae6fc14330ea10ef1eec2d7136217dd3be3582 /dts/Bindings/memory-controllers
parent574eed3f6fcf056aa4c9e46c4b5224e3f7844d8d (diff)
downloadbarebox-17a537847ed3b1c0fcae46a43e1374868dc7dae6.tar.gz
barebox-17a537847ed3b1c0fcae46a43e1374868dc7dae6.tar.xz
dts: update to v5.5-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml3
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml9
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml3
3 files changed, 10 insertions, 5 deletions
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
index 30d9fb193d..22a94b6fdb 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
@@ -60,7 +60,8 @@ patternProperties:
maximum: 1066000000
nvidia,emem-configuration:
- $ref: /schemas/types.yaml#/definitions/uint32-array
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"15.6.1 MC Registers" in the TRM.
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
index 7fe0ca14e3..e4135bac69 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
@@ -56,7 +56,8 @@ patternProperties:
maximum: 900000000
nvidia,emc-auto-cal-interval:
- $ref: /schemas/types.yaml#/definitions/uint32
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
description:
Pad calibration interval in microseconds.
minimum: 0
@@ -78,7 +79,8 @@ patternProperties:
Mode Register 0.
nvidia,emc-zcal-cnt-long:
- $ref: /schemas/types.yaml#/definitions/uint32
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of EMC clocks to wait before issuing any commands after
sending ZCAL_MRW_CMD.
@@ -96,7 +98,8 @@ patternProperties:
FBIO "read" FIFO periodic resetting enabled.
nvidia,emc-configuration:
- $ref: /schemas/types.yaml#/definitions/uint32-array
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers
(see section "18.13.2 EMC Registers" in the TRM) whose values
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
index 84fd57bcf0..4b9196c832 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
@@ -77,7 +77,8 @@ patternProperties:
maximum: 900000000
nvidia,emem-configuration:
- $ref: /schemas/types.yaml#/definitions/uint32-array
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"18.13.1 MC Registers" in the TRM.