diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-08 07:35:17 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-12-10 08:48:40 +0100 |
| commit | 6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 (patch) | |
| tree | bcf5e71df4472e374d03cc15ca22b4f841d9c73d /dts/Bindings/memory-controllers | |
| parent | 8e2fd5380a4fd7cee428513dc8eab068912b49f1 (diff) | |
| download | barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.gz barebox-6e6d9a2ff045f09d5a03e876becea5e6a1dabe90.tar.xz | |
dts: update to v4.4-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
| -rw-r--r-- | dts/Bindings/memory-controllers/arm,pl172.txt | 8 | ||||
| -rw-r--r-- | dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt | 16 | ||||
| -rw-r--r-- | dts/Bindings/memory-controllers/renesas-memory-controllers.txt | 6 |
3 files changed, 24 insertions, 6 deletions
diff --git a/dts/Bindings/memory-controllers/arm,pl172.txt b/dts/Bindings/memory-controllers/arm,pl172.txt index e6df32f998..22b77ee02f 100644 --- a/dts/Bindings/memory-controllers/arm,pl172.txt +++ b/dts/Bindings/memory-controllers/arm,pl172.txt @@ -1,8 +1,9 @@ -* Device tree bindings for ARM PL172 MultiPort Memory Controller +* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller Required properties: -- compatible: "arm,pl172", "arm,primecell" +- compatible: Must be "arm,primecell" and exactly one from + "arm,pl172", "arm,pl175" or "arm,pl176". - reg: Must contains offset/length value for controller. @@ -56,7 +57,8 @@ Optional child cs node config properties: - mpmc,extended-wait: Enable extended wait. -- mpmc,buffer-enable: Enable write buffer. +- mpmc,buffer-enable: Enable write buffer, option is not supported by + PL175 and PL176 controllers. - mpmc,write-protect: Enable write protect. diff --git a/dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt new file mode 100644 index 0000000000..049675944b --- /dev/null +++ b/dts/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt @@ -0,0 +1,16 @@ +Calxeda DDR memory controller + +Properties: +- compatible : Should be: + - "calxeda,hb-ddr-ctrl" for ECX-1000 + - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 +- reg : Address and size for DDR controller registers. +- interrupts : Interrupt for DDR controller. + +Example: + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; diff --git a/dts/Bindings/memory-controllers/renesas-memory-controllers.txt b/dts/Bindings/memory-controllers/renesas-memory-controllers.txt index c64b7925cd..9f78e6c827 100644 --- a/dts/Bindings/memory-controllers/renesas-memory-controllers.txt +++ b/dts/Bindings/memory-controllers/renesas-memory-controllers.txt @@ -24,9 +24,9 @@ Required properties: Optional properties: - interrupts: Must contain a list of interrupt specifiers for memory controller interrupts, if available. - - interrupts-names: Must contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Valid interrupt names are: + - interrupt-names: Must contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: - "sec" (secure interrupt) - "temp" (normal (temperature) interrupt) - power-domains: Must contain a reference to the PM domain that the memory |