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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-21 09:53:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-21 09:53:29 +0200 |
| commit | 80700ad5bfd490f86b3e49ed8675e96218bbcd4c (patch) | |
| tree | 9d9e7d81c29d021eed65be978450d05727d5aae5 /dts/Bindings/memory-controllers | |
| parent | 4eefe44b3dea5b8eb778938e8f75c339ac5119fc (diff) | |
| download | barebox-80700ad5bfd490f86b3e49ed8675e96218bbcd4c.tar.gz barebox-80700ad5bfd490f86b3e49ed8675e96218bbcd4c.tar.xz | |
dts: update to v5.18-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
11 files changed, 15 insertions, 13 deletions
diff --git a/dts/Bindings/memory-controllers/brcm,dpfe-cpu.yaml b/dts/Bindings/memory-controllers/brcm,dpfe-cpu.yaml index 769f132500..08cbdcddfe 100644 --- a/dts/Bindings/memory-controllers/brcm,dpfe-cpu.yaml +++ b/dts/Bindings/memory-controllers/brcm,dpfe-cpu.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: DDR PHY Front End (DPFE) for Broadcom STB maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> - Markus Mayer <mmayer@broadcom.com> properties: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml index f3e62ee071..1daa665924 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR2 SDRAM AC timing parameters for a given speed-bin maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml index dd2141cad8..9d78f14060 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR2 SDRAM compliant to JEDEC JESD209-2 maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml index 97c3e988af..5c6512c1e1 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR3 SDRAM AC timing parameters for a given speed-bin maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml index c542f32c39..48908a1947 100644 --- a/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/dts/Bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml b/dts/Bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml index 14a6bc8f42..9249624c4f 100644 --- a/dts/Bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml +++ b/dts/Bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml @@ -8,7 +8,7 @@ title: Marvell MVEBU SDRAM controller maintainers: - Jan Luebbe <jlu@pengutronix.de> - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> properties: compatible: diff --git a/dts/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml b/dts/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml index 9566b3421f..0c511ab906 100644 --- a/dts/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml +++ b/dts/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> description: | The DDR controller of the AR7xxx and AR9xxx families provides an interface to diff --git a/dts/Bindings/memory-controllers/renesas,h8300-bsc.yaml b/dts/Bindings/memory-controllers/renesas,h8300-bsc.yaml index 2b18cef995..514b2c5f88 100644 --- a/dts/Bindings/memory-controllers/renesas,h8300-bsc.yaml +++ b/dts/Bindings/memory-controllers/renesas,h8300-bsc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: H8/300 bus controller maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> - Yoshinori Sato <ysato@users.sourceforge.jp> properties: diff --git a/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml index f152243f6b..098348b2b8 100644 --- a/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/dts/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -9,7 +9,7 @@ title: | Controller device maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> - Lukasz Luba <lukasz.luba@arm.com> description: | diff --git a/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml index fb7ae38a9c..f46e95704f 100644 --- a/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml +++ b/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys IntelliDDR Multi Protocol memory controller maintainers: - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> - Manish Narani <manish.narani@xilinx.com> - Michal Simek <michal.simek@xilinx.com> @@ -24,9 +24,9 @@ description: | properties: compatible: enum: + - snps,ddrc-3.80a - xlnx,zynq-ddrc-a05 - xlnx,zynqmp-ddrc-2.40a - - snps,ddrc-3.80a interrupts: maxItems: 1 @@ -43,7 +43,9 @@ allOf: properties: compatible: contains: - const: xlnx,zynqmp-ddrc-2.40a + enum: + - snps,ddrc-3.80a + - xlnx,zynqmp-ddrc-2.40a then: required: - interrupts diff --git a/dts/Bindings/memory-controllers/ti,da8xx-ddrctl.yaml b/dts/Bindings/memory-controllers/ti,da8xx-ddrctl.yaml index 9ed51185ff..382ddab60f 100644 --- a/dts/Bindings/memory-controllers/ti,da8xx-ddrctl.yaml +++ b/dts/Bindings/memory-controllers/ti,da8xx-ddrctl.yaml @@ -8,7 +8,7 @@ title: Texas Instruments da8xx DDR2/mDDR memory controller maintainers: - Bartosz Golaszewski <bgolaszewski@baylibre.com> - - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Krzysztof Kozlowski <krzk@kernel.org> description: | Documentation: |