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authorSascha Hauer <s.hauer@pengutronix.de>2015-12-08 07:33:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-12-10 08:48:39 +0100
commita05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch)
tree69bb9a750c3f22308887a30b37e946b2738e33d4 /dts/Bindings/memory-controllers
parent48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff)
downloadbarebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz
barebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.xz
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
-rw-r--r--dts/Bindings/memory-controllers/arm,pl172.txt125
-rw-r--r--dts/Bindings/memory-controllers/fsl/ifc.txt3
-rw-r--r--dts/Bindings/memory-controllers/synopsys.txt4
3 files changed, 132 insertions, 0 deletions
diff --git a/dts/Bindings/memory-controllers/arm,pl172.txt b/dts/Bindings/memory-controllers/arm,pl172.txt
new file mode 100644
index 000000000..e6df32f99
--- /dev/null
+++ b/dts/Bindings/memory-controllers/arm,pl172.txt
@@ -0,0 +1,125 @@
+* Device tree bindings for ARM PL172 MultiPort Memory Controller
+
+Required properties:
+
+- compatible: "arm,pl172", "arm,primecell"
+
+- reg: Must contains offset/length value for controller.
+
+- #address-cells: Must be 2. The partition number has to be encoded in the
+ first address cell and it may accept values 0..N-1
+ (N - total number of partitions). The second cell is the
+ offset into the partition.
+
+- #size-cells: Must be set to 1.
+
+- ranges: Must contain one or more chip select memory regions.
+
+- clocks: Must contain references to controller clocks.
+
+- clock-names: Must contain "mpmcclk" and "apb_pclk".
+
+- clock-ranges: Empty property indicating that child nodes can inherit
+ named clocks. Required only if clock tree data present
+ in device tree.
+ See clock-bindings.txt
+
+Child chip-select (cs) nodes contain the memory devices nodes connected to
+such as NOR (e.g. cfi-flash) and NAND.
+
+Required child cs node properties:
+
+- #address-cells: Must be 2.
+
+- #size-cells: Must be 1.
+
+- ranges: Empty property indicating that child nodes can inherit
+ memory layout.
+
+- clock-ranges: Empty property indicating that child nodes can inherit
+ named clocks. Required only if clock tree data present
+ in device tree.
+
+- mpmc,cs: Chip select number. Indicates to the pl0172 driver
+ which chipselect is used for accessing the memory.
+
+- mpmc,memory-width: Width of the chip select memory. Must be equal to
+ either 8, 16 or 32.
+
+Optional child cs node config properties:
+
+- mpmc,async-page-mode: Enable asynchronous page mode.
+
+- mpmc,cs-active-high: Set chip select polarity to active high.
+
+- mpmc,byte-lane-low: Set byte lane state to low.
+
+- mpmc,extended-wait: Enable extended wait.
+
+- mpmc,buffer-enable: Enable write buffer.
+
+- mpmc,write-protect: Enable write protect.
+
+Optional child cs node timing properties:
+
+- mpmc,write-enable-delay: Delay from chip select assertion to write
+ enable (WE signal) in nano seconds.
+
+- mpmc,output-enable-delay: Delay from chip select assertion to output
+ enable (OE signal) in nano seconds.
+
+- mpmc,write-access-delay: Delay from chip select assertion to write
+ access in nano seconds.
+
+- mpmc,read-access-delay: Delay from chip select assertion to read
+ access in nano seconds.
+
+- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
+ accesses in nano seconds.
+
+- mpmc,turn-round-delay: Delay between access to memory banks in nano
+ seconds.
+
+If any of the above timing parameters are absent, current parameter value will
+be taken from the corresponding HW reg.
+
+Example for pl172 with nor flash on chip select 0 shown below.
+
+emc: memory-controller@40005000 {
+ compatible = "arm,pl172", "arm,primecell";
+ reg = <0x40005000 0x1000>;
+ clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
+ clock-names = "mpmcclk", "apb_pclk";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1c000000 0x1000000
+ 1 0 0x1d000000 0x1000000
+ 2 0 0x1e000000 0x1000000
+ 3 0 0x1f000000 0x1000000>;
+
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ mpmc,cs = <0>;
+ mpmc,memory-width = <16>;
+ mpmc,byte-lane-low;
+ mpmc,write-enable-delay = <0>;
+ mpmc,output-enable-delay = <0>;
+ mpmc,read-enable-delay = <70>;
+ mpmc,page-mode-read-delay = <70>;
+
+ flash@0,0 {
+ compatible = "sst,sst39vf320", "cfi-flash";
+ reg = <0 0 0x400000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "data";
+ reg = <0 0x400000>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/memory-controllers/fsl/ifc.txt b/dts/Bindings/memory-controllers/fsl/ifc.txt
index d5e370450..89427b018 100644
--- a/dts/Bindings/memory-controllers/fsl/ifc.txt
+++ b/dts/Bindings/memory-controllers/fsl/ifc.txt
@@ -18,6 +18,8 @@ Properties:
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
+- little-endian : If this property is absent, the big-endian mode will
+ be in use as default for registers.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
@@ -34,6 +36,7 @@ Example:
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
+ little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
diff --git a/dts/Bindings/memory-controllers/synopsys.txt b/dts/Bindings/memory-controllers/synopsys.txt
index f9c645414..a43d26d41 100644
--- a/dts/Bindings/memory-controllers/synopsys.txt
+++ b/dts/Bindings/memory-controllers/synopsys.txt
@@ -1,5 +1,9 @@
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+This controller has an optional ECC support in half-bus width (16-bit)
+configuration. The ECC controller corrects one bit error and detects
+two bit errors.
+
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area