diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-02-27 09:40:19 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-01 14:29:51 +0100 |
commit | a9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch) | |
tree | 35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/Bindings/memory-controllers | |
parent | 5ba0e42cb24afdf59d48930daf495c148312fc67 (diff) | |
download | barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.xz |
dts: update to v4.16-rc1
Also includeded:
ARM: dts: am33xx: do not delete no longer existing clocks
Several clocks are removed from the am33xx dts files with v4.16-rc1.
Remove the corresponding /delete-node/ directives aswell to avoid
dtc breakage.
Also included:
ARM: dts: imx6qdl: SolidRun: Fix upstream include
Upstream dts file way renamed, so change include name accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/memory-controllers')
-rw-r--r-- | dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/memory-controllers/ti-aemif.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/memory-controllers/ti/emif.txt | 17 |
3 files changed, 19 insertions, 2 deletions
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt index 8dbe47013c..14968b048c 100644 --- a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt +++ b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.txt @@ -12,6 +12,8 @@ Required properties: - clock-names: Must include the following entries: - mc: the module's clock input - interrupts: The interrupt outputs from the controller. + +Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210: - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines the SWGROUP of the master. diff --git a/dts/Bindings/memory-controllers/ti-aemif.txt b/dts/Bindings/memory-controllers/ti-aemif.txt index 9592717f48..190437a0c1 100644 --- a/dts/Bindings/memory-controllers/ti-aemif.txt +++ b/dts/Bindings/memory-controllers/ti-aemif.txt @@ -138,7 +138,7 @@ from the corresponding HW reg. Example for aemif, davinci nand and nor flash chip select shown below. -memory-controller@21000A00 { +memory-controller@21000a00 { compatible = "ti,davinci-aemif"; #address-cells = <2>; #size-cells = <1>; diff --git a/dts/Bindings/memory-controllers/ti/emif.txt b/dts/Bindings/memory-controllers/ti/emif.txt index 152eeccbde..621b41c79f 100644 --- a/dts/Bindings/memory-controllers/ti/emif.txt +++ b/dts/Bindings/memory-controllers/ti/emif.txt @@ -23,6 +23,13 @@ Required properties: the value shall be "emif<n>" where <n> is the number of the EMIF instance with base 1. +Required only for "ti,emif-am3352" and "ti,emif-am4372": +- sram : Phandles for generic sram driver nodes, + first should be type 'protect-exec' for the driver to use to copy + and run PM functions, second should be regular pool to be used for + data region for code. See Documentation/devicetree/bindings/sram/sram.txt + for more details. + Optional properties: - cs1-used : Have this property if CS1 of this EMIF instance has a memory part attached to it. If there is a memory @@ -44,7 +51,7 @@ Optional properties: - hw-caps-temp-alert : Have this property if the controller has capability for generating SDRAM temperature alerts -Example: +-Examples: emif1: emif@4c000000 { compatible = "ti,emif-4d"; @@ -56,3 +63,11 @@ emif1: emif@4c000000 { hw-caps-ll-interface; hw-caps-temp-alert; }; + +/* From am33xx.dtsi */ +emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4C000000 0x1000>; + sram = <&pm_sram_code + &pm_sram_data>; +}; |