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author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-07 09:48:28 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-11-08 08:57:14 +0100 |
commit | 646d1a09f05689a3a4781112a3b3e4747d0ba231 (patch) | |
tree | fe48ab82140e06e495051098fde1d97a4b1e56d5 /dts/Bindings/mips/mscc.txt | |
parent | ebc406c1ab2be0e6002e1d8ccbc5c1377a882895 (diff) | |
download | barebox-646d1a09f05689a3a4781112a3b3e4747d0ba231.tar.gz barebox-646d1a09f05689a3a4781112a3b3e4747d0ba231.tar.xz |
dts: update to v4.20-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mips/mscc.txt')
-rw-r--r-- | dts/Bindings/mips/mscc.txt | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/dts/Bindings/mips/mscc.txt b/dts/Bindings/mips/mscc.txt index ae15ec3335..bc817e9846 100644 --- a/dts/Bindings/mips/mscc.txt +++ b/dts/Bindings/mips/mscc.txt @@ -41,3 +41,19 @@ Example: compatible = "mscc,ocelot-cpu-syscon", "syscon"; reg = <0x70000000 0x2c>; }; + +o HSIO regs: + +The SoC has a few registers (HSIO) handling miscellaneous functionalities: +configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and +status, SerDes muxing and a thermal sensor. + +Required properties: +- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd" +- reg : Should contain registers location and length + +Example: + syscon@10d0000 { + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd"; + reg = <0x10d0000 0x10000>; + }; |