dts: update to v5.0-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 30 insertions, 1 deletions

diff --git a/dts/Bindings/misc/fsl,qoriq-mc.txt b/dts/Bindings/misc/fsl,qoriq-mc.txt
index 01fdc33a41..bb7e896cb6 100644
--- a/dts/Bindings/misc/fsl,qoriq-mc.txt
+++ b/dts/Bindings/misc/fsl,qoriq-mc.txt
@@ -10,7 +10,7 @@ such as network interfaces, crypto accelerator instances, L2 switches,
 etc.
 
 For an overview of the DPAA2 architecture and fsl-mc bus see:
-Documentation/networking/dpaa2/overview.rst
+Documentation/networking/device_drivers/freescale/dpaa2/overview.rst
 
 As described in the above overview, all DPAA2 objects in a DPRC share the
 same hardware "isolation context" and a 10-bit value called an ICID
diff --git a/dts/Bindings/misc/pvpanic-mmio.txt b/dts/Bindings/misc/pvpanic-mmio.txt
new file mode 100644
index 0000000000..985e907367
--- /dev/null
+++ b/dts/Bindings/misc/pvpanic-mmio.txt
@@ -0,0 +1,29 @@
+* QEMU PVPANIC MMIO Configuration bindings
+
+QEMU's emulation / virtualization targets provide the following PVPANIC
+MMIO Configuration interface on the "virt" machine.
+type:
+
+- a read-write, 16-bit wide data register.
+
+QEMU exposes the data register to guests as memory mapped registers.
+
+Required properties:
+
+- compatible: "qemu,pvpanic-mmio".
+- reg: the MMIO region used by the device.
+  * Bytes 0x0  Write panic event to the reg when guest OS panics.
+  * Bytes 0x1  Reserved.
+
+Example:
+
+/ {
+        #size-cells = <0x2>;
+        #address-cells = <0x2>;
+
+        pvpanic-mmio@9060000 {
+                compatible = "qemu,pvpanic-mmio";
+                reg = <0x0 0x9060000 0x0 0x2>;
+        };
+};
+