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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:26:15 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-01-10 08:48:45 +0100 |
| commit | a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab (patch) | |
| tree | 35f886d87a77df7bac8a587a04647691db541a2e /dts/Bindings/mmc/sdhci-cadence.txt | |
| parent | 81462901ce3d677ce318150f7027e2ce1cf97c41 (diff) | |
| download | barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.gz barebox-a40531fb3c11dc4ee8cca43c91b471da1fd3c1ab.tar.xz | |
dts: update to v4.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mmc/sdhci-cadence.txt')
| -rw-r--r-- | dts/Bindings/mmc/sdhci-cadence.txt | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/dts/Bindings/mmc/sdhci-cadence.txt b/dts/Bindings/mmc/sdhci-cadence.txt new file mode 100644 index 0000000000..c0f37cb41a --- /dev/null +++ b/dts/Bindings/mmc/sdhci-cadence.txt @@ -0,0 +1,32 @@ +* Cadence SD/SDIO/eMMC Host Controller + +Required properties: +- compatible: should be one of the following: + "cdns,sd4hc" - default of the IP + "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs +- reg: offset and length of the register set for the device. +- interrupts: a single interrupt specifier. +- clocks: phandle to the input clock. + +Optional properties: +For eMMC configuration, supported speed modes are not indicated by the SDHCI +Capabilities Register. Instead, the following properties should be specified +if supported. See mmc.txt for details. +- mmc-ddr-1_8v +- mmc-ddr-1_2v +- mmc-hs200-1_8v +- mmc-hs200-1_2v +- mmc-hs400-1_8v +- mmc-hs400-1_2v + +Example: + emmc: sdhci@5a000000 { + compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; + reg = <0x5a000000 0x400>; + interrupts = <0 78 4>; + clocks = <&clk 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; |