dts: update to v5.9-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

9 files changed, 235 insertions, 133 deletions

diff --git a/dts/Bindings/mtd/arasan,nand-controller.yaml b/dts/Bindings/mtd/arasan,nand-controller.yaml
index cb9794edff..b328769332 100644
--- a/dts/Bindings/mtd/arasan,nand-controller.yaml
+++ b/dts/Bindings/mtd/arasan,nand-controller.yaml
@@ -14,12 +14,10 @@ maintainers:
 
 properties:
   compatible:
-    oneOf:
-      - items:
-        - enum:
+    items:
+      - enum:
           - xlnx,zynqmp-nand-controller
-        - enum:
-          - arasan,nfc-v3p10
+      - const: arasan,nfc-v3p10
 
   reg:
     maxItems: 1
diff --git a/dts/Bindings/mtd/davinci-nand.txt b/dts/Bindings/mtd/davinci-nand.txt
index cfb18abe60..edebeae1f5 100644
--- a/dts/Bindings/mtd/davinci-nand.txt
+++ b/dts/Bindings/mtd/davinci-nand.txt
@@ -4,8 +4,8 @@ This file provides information, what the device node for the davinci/keystone
 NAND interface contains.
 
 Documentation:
-Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
-Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
+Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
+Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
 
 Required properties:
 
diff --git a/dts/Bindings/mtd/fsl-upm-nand.txt b/dts/Bindings/mtd/fsl-upm-nand.txt
index fce4894f5a..25f07c1f9e 100644
--- a/dts/Bindings/mtd/fsl-upm-nand.txt
+++ b/dts/Bindings/mtd/fsl-upm-nand.txt
@@ -7,14 +7,16 @@ Required properties:
 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
 
 Optional properties:
-- fsl,upm-wait-flags : add chip-dependent short delays after running the
-	UPM pattern (0x1), after writing a data byte (0x2) or after
-	writing out a buffer (0x4).
 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
 	The corresponding address lines are used to select the chip.
 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
 	(R/B#). For multi-chip devices, "n" GPIO definitions are required
 	according to the number of chips.
+
+Deprecated properties:
+- fsl,upm-wait-flags : add chip-dependent short delays after running the
+	UPM pattern (0x1), after writing a data byte (0x2) or after
+	writing out a buffer (0x4).
 - chip-delay : chip dependent delay for transferring data from array to
 	read registers (tR). Required if property "gpios" is not used
 	(R/B# pins not connected).
@@ -52,8 +54,6 @@ upm@3,0 {
 	fsl,upm-cmd-offset = <0x08>;
 	/* Multi-chip NAND device */
 	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
-	fsl,upm-wait-flags = <0x5>;
-	chip-delay = <25>; // in micro-seconds
 
 	nand@0 {
 		#address-cells = <1>;
diff --git a/dts/Bindings/mtd/gpmi-nand.txt b/dts/Bindings/mtd/gpmi-nand.txt
deleted file mode 100644
index 393588385c..0000000000
--- a/dts/Bindings/mtd/gpmi-nand.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-* Freescale General-Purpose Media Interface (GPMI)
-
-The GPMI nand controller provides an interface to control the
-NAND flash chips.
-
-Required properties:
-  - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
-    * imx23
-    * imx28
-    * imx6q
-    * imx6sx
-    * imx7d
-  - reg : should contain registers location and length for gpmi and bch.
-  - reg-names: Should contain the reg names "gpmi-nand" and "bch"
-  - interrupts : BCH interrupt number.
-  - interrupt-names : Should be "bch".
-  - dmas: DMA specifier, consisting of a phandle to DMA controller node
-    and GPMI DMA channel ID.
-    Refer to dma.txt and fsl-mxs-dma.txt for details.
-  - dma-names: Must be "rx-tx".
-  - clocks : clocks phandle and clock specifier corresponding to each clock
-    specified in clock-names.
-  - clock-names : The "gpmi_io" clock is always required. Which clocks are
-    exactly required depends on chip:
-    * imx23/imx28 : "gpmi_io"
-    * imx6q/sx : "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"
-    * imx7d : "gpmi_io", "gpmi_bch_apb"
-
-Optional properties:
-  - nand-on-flash-bbt: boolean to enable on flash bbt option if not
-                       present false
-  - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
-                       strength required. The required ECC strength is
-                       automatically discoverable for some flash
-                       (e.g., according to the ONFI standard).
-                       However, note that if this strength is not
-                       discoverable or this property is not enabled,
-                       the software may chooses an implementation-defined
-                       ECC scheme.
-  - fsl,no-blockmark-swap: Don't swap the bad block marker from the OOB
-                       area with the byte in the data area but rely on the
-                       flash based BBT for identifying bad blocks.
-                       NOTE: this is only valid in conjunction with
-                             'nand-on-flash-bbt'.
-                       WARNING: on i.MX28 blockmark swapping cannot be
-                       disabled for the BootROM in the FCB. Thus,
-                       partitions written from Linux with this feature
-                       turned on may not be accessible by the BootROM
-                       code.
-  - nand-ecc-strength: integer representing the number of bits to correct
-                       per ECC step. Needs to be a multiple of 2.
-  - nand-ecc-step-size: integer representing the number of data bytes
-                       that are covered by a single ECC step. The driver
-                       supports 512 and 1024.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Examples:
-
-gpmi-nand@8000c000 {
-	compatible = "fsl,imx28-gpmi-nand";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	reg = <0x8000c000 2000>, <0x8000a000 2000>;
-	reg-names = "gpmi-nand", "bch";
-	interrupts = <41>;
-	interrupt-names = "bch";
-	dmas = <&dma_apbh 4>;
-	dma-names = "rx-tx";
-
-	partition@0 {
-	...
-	};
-};
diff --git a/dts/Bindings/mtd/gpmi-nand.yaml b/dts/Bindings/mtd/gpmi-nand.yaml
new file mode 100644
index 0000000000..3201372b7f
--- /dev/null
+++ b/dts/Bindings/mtd/gpmi-nand.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale General-Purpose Media Interface (GPMI) binding
+
+maintainers:
+  - Han Xu <han.xu@nxp.com>
+
+allOf:
+  - $ref: "nand-controller.yaml"
+
+description: |
+  The GPMI nand controller provides an interface to control the NAND
+  flash chips. The device tree may optionally contain sub-nodes
+  describing partitions of the address space. See partition.txt for
+  more detail.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx23-gpmi-nand
+      - fsl,imx28-gpmi-nand
+      - fsl,imx6q-gpmi-nand
+      - fsl,imx6sx-gpmi-nand
+      - fsl,imx7d-gpmi-nand
+
+  reg:
+    items:
+      - description: Address and length of gpmi block.
+      - description: Address and length of bch block.
+
+  reg-names:
+    items:
+      - const: gpmi-nand
+      - const: bch
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    const: bch
+
+  dmas:
+    maxItems: 1
+
+  dma-names:
+    const: rx-tx
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+    items:
+      - description: SoC gpmi io clock
+      - description: SoC gpmi apb clock
+      - description: SoC gpmi bch clock
+      - description: SoC gpmi bch apb clock
+      - description: SoC per1 bch clock
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+    items:
+      - const: gpmi_io
+      - const: gpmi_apb
+      - const: gpmi_bch
+      - const: gpmi_bch_apb
+      - const: per1_bch
+
+  fsl,use-minimum-ecc:
+    type: boolean
+    description: |
+      Protect this NAND flash with the minimum ECC strength required.
+      The required ECC strength is automatically discoverable for some
+      flash (e.g., according to the ONFI standard). However, note that
+      if this strength is not discoverable or this property is not enabled,
+      the software may chooses an implementation-defined ECC scheme.
+
+  fsl,no-blockmark-swap:
+    type: boolean
+    description: |
+      Don't swap the bad block marker from the OOB area with the byte in
+      the data area but rely on the flash based BBT for identifying bad blocks.
+      NOTE: this is only valid in conjunction with 'nand-on-flash-bbt'.
+      WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
+      in the FCB. Thus, partitions written from Linux with this feature turned
+      on may not be accessible by the BootROM code.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - dmas
+  - dma-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand-controller@8000c000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx28-gpmi-nand";
+        reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+        reg-names = "gpmi-nand", "bch";
+        interrupts = <41>;
+        interrupt-names = "bch";
+        clocks = <&clks 50>;
+        clock-names = "gpmi_io";
+        dmas = <&dma_apbh 4>;
+        dma-names = "rx-tx";
+    };
diff --git a/dts/Bindings/mtd/mxc-nand.txt b/dts/Bindings/mtd/mxc-nand.txt
deleted file mode 100644
index 2857c628fb..0000000000
--- a/dts/Bindings/mtd/mxc-nand.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Freescale's mxc_nand
-
-Required properties:
-- compatible: "fsl,imxXX-nand"
-- reg: address range of the nfc block
-- interrupts: irq to be used
-- nand-bus-width: see nand-controller.yaml
-- nand-ecc-mode: see nand-controller.yaml
-- nand-on-flash-bbt: see nand-controller.yaml
-
-Example:
-
-	nand@d8000000 {
-		compatible = "fsl,imx27-nand";
-		reg = <0xd8000000 0x1000>;
-		interrupts = <29>;
-		nand-bus-width = <8>;
-		nand-ecc-mode = "hw";
-	};
diff --git a/dts/Bindings/mtd/mxc-nand.yaml b/dts/Bindings/mtd/mxc-nand.yaml
new file mode 100644
index 0000000000..73b86f2226
--- /dev/null
+++ b/dts/Bindings/mtd/mxc-nand.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mxc-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale's mxc_nand binding
+
+maintainers:
+  - Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+
+allOf:
+  - $ref: "nand-controller.yaml"
+
+properties:
+  compatible:
+    const: fsl,imx27-nand
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand-controller@d8000000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx27-nand";
+        reg = <0xd8000000 0x1000>;
+        interrupts = <29>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+    };
diff --git a/dts/Bindings/mtd/nand-controller.yaml b/dts/Bindings/mtd/nand-controller.yaml
index cde7c4d79e..40fc5b0b2b 100644
--- a/dts/Bindings/mtd/nand-controller.yaml
+++ b/dts/Bindings/mtd/nand-controller.yaml
@@ -114,6 +114,13 @@ patternProperties:
         description:
           Contains the native Ready/Busy IDs.
 
+      rb-gpios:
+        description:
+          Contains one or more GPIO descriptor (the numper of descriptor
+          depends on the number of R/B pins exposed by the flash) for the
+          Ready/Busy pins. Active state refers to the NAND ready state and
+          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
+
     required:
       - reg
 
diff --git a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml
index b059267f6d..28a08ff407 100644
--- a/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml
+++ b/dts/Bindings/mtd/st,stm32-fmc2-nand.yaml
@@ -9,32 +9,19 @@ title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
 maintainers:
   - Christophe Kerello <christophe.kerello@st.com>
 
-allOf:
-  - $ref: "nand-controller.yaml#"
-
 properties:
   compatible:
-    const: st,stm32mp15-fmc2
+    enum:
+      - st,stm32mp15-fmc2
+      - st,stm32mp1-fmc2-nfc
 
   reg:
-    items:
-      - description: Registers
-      - description: Chip select 0 data
-      - description: Chip select 0 command
-      - description: Chip select 0 address space
-      - description: Chip select 1 data
-      - description: Chip select 1 command
-      - description: Chip select 1 address space
+    minItems: 6
+    maxItems: 7
 
   interrupts:
     maxItems: 1
 
-  clocks:
-    maxItems: 1
-
-  resets:
-    maxItems: 1
-
   dmas:
     items:
       - description: tx DMA channel
@@ -55,13 +42,57 @@ patternProperties:
         const: 512
 
       nand-ecc-strength:
-        enum: [1, 4 ,8 ]
+        enum: [1, 4, 8]
+
+allOf:
+  - $ref: "nand-controller.yaml#"
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32mp15-fmc2
+    then:
+      properties:
+        reg:
+          items:
+            - description: Registers
+            - description: Chip select 0 data
+            - description: Chip select 0 command
+            - description: Chip select 0 address space
+            - description: Chip select 1 data
+            - description: Chip select 1 command
+            - description: Chip select 1 address space
+
+        clocks:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+      required:
+        - clocks
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32mp1-fmc2-nfc
+    then:
+      properties:
+        reg:
+          items:
+            - description: Chip select 0 data
+            - description: Chip select 0 command
+            - description: Chip select 0 address space
+            - description: Chip select 1 data
+            - description: Chip select 1 command
+            - description: Chip select 1 address space
 
 required:
   - compatible
   - reg
   - interrupts
-  - clocks
 
 examples:
   - |
@@ -77,13 +108,13 @@ examples:
             <0x81000000 0x1000>,
             <0x89010000 0x1000>,
             <0x89020000 0x1000>;
-            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-            dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
-                   <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
-                   <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
-            dma-names = "tx", "rx", "ecc";
-            clocks = <&rcc FMC_K>;
-            resets = <&rcc FMC_R>;
+      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+      dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+             <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+             <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+      dma-names = "tx", "rx", "ecc";
+      clocks = <&rcc FMC_K>;
+      resets = <&rcc FMC_R>;
       #address-cells = <1>;
       #size-cells = <0>;