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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
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| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-10-18 10:10:24 +0200 |
| commit | bfbf18d991756858337f7700e8ff0a6f0dc31afc (patch) | |
| tree | cf3568de4fdff1891e277507f08f49a871682706 /dts/Bindings/mtd | |
| parent | 834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff) | |
| download | barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz | |
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/mtd')
| -rw-r--r-- | dts/Bindings/mtd/nand.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/dts/Bindings/mtd/nand.txt b/dts/Bindings/mtd/nand.txt index 3733300de8..b056016000 100644 --- a/dts/Bindings/mtd/nand.txt +++ b/dts/Bindings/mtd/nand.txt @@ -35,6 +35,15 @@ Optional NAND chip properties: - nand-ecc-step-size: integer representing the number of data bytes that are covered by a single ECC step. +- nand-ecc-maximize: boolean used to specify that you want to maximize ECC + strength. The maximum ECC strength is both controller and + chip dependent. The controller side has to select the ECC + config providing the best strength and taking the OOB area + size constraint into account. + This is particularly useful when only the in-band area is + used by the upper layers, and you want to make your NAND + as reliable as possible. + The ECC strength and ECC step size properties define the correction capability of a controller. Together, they say a controller can correct "{strength} bit errors per {size} bytes". |