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authorSascha Hauer <s.hauer@pengutronix.de>2016-06-13 07:31:05 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-06-13 07:31:05 +0200
commitc672e87588a9db0b2f23938964d882c38cb21f2c (patch)
treee8d54ee83c1bfed55681bd94e5827f248ab8de42 /dts/Bindings/net/mediatek-net.txt
parentad85fd3b3173b72eda09114ec6722639a4b33c25 (diff)
downloadbarebox-c672e87588a9db0b2f23938964d882c38cb21f2c.tar.gz
barebox-c672e87588a9db0b2f23938964d882c38cb21f2c.tar.xz
dts: update to v4.6-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/net/mediatek-net.txt')
-rw-r--r--dts/Bindings/net/mediatek-net.txt7
1 files changed, 5 insertions, 2 deletions
diff --git a/dts/Bindings/net/mediatek-net.txt b/dts/Bindings/net/mediatek-net.txt
index 5ca79290e..32eaaca04 100644
--- a/dts/Bindings/net/mediatek-net.txt
+++ b/dts/Bindings/net/mediatek-net.txt
@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
Required properties:
- compatible: Should be "mediatek,mt7623-eth"
- reg: Address and length of the register set for the device
-- interrupts: Should contain the frame engines interrupt
+- interrupts: Should contain the three frame engines interrupts in numeric
+ order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
"ethif", "esw", "gp2", "gp1"
@@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
<&ethsys CLK_ETHSYS_GP2>,
<&ethsys CLK_ETHSYS_GP1>;
clock-names = "ethif", "esw", "gp2", "gp1";
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
reset-names = "eth";