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authorSascha Hauer <s.hauer@pengutronix.de>2017-03-10 08:56:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-03-10 08:56:15 +0100
commit957bb6b6bcebc4c36f5f284dfb58d489e81016c6 (patch)
tree593d098617017987daaf8ce339e0eb29ea09fdde /dts/Bindings/net/phy.txt
parentcc2392cf4f2d5208be427e9ffdeafba192f05cbe (diff)
downloadbarebox-957bb6b6bcebc4c36f5f284dfb58d489e81016c6.tar.gz
barebox-957bb6b6bcebc4c36f5f284dfb58d489e81016c6.tar.xz
dts: update to v4.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/net/phy.txt')
-rw-r--r--dts/Bindings/net/phy.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt
index fb5056b226..b55857696f 100644
--- a/dts/Bindings/net/phy.txt
+++ b/dts/Bindings/net/phy.txt
@@ -39,6 +39,10 @@ Optional Properties:
- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes swapped.
+- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
+ TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
+ bootstrap configuration caused by issues in PCB layout design.
+
- eee-broken-100tx:
- eee-broken-1000t:
- eee-broken-10gt: