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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-02-13 09:26:03 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-02-13 09:26:03 +0100 |
commit | a06513273fc18c16b5081ddd80ce14b7de37cf6e (patch) | |
tree | d4f3eaf209d8710bd4fd2f17377dc1573b43406b /dts/Bindings/net | |
parent | a9ba8a1d0d5c164b6962f7b80f08278302f54182 (diff) | |
parent | cbf19c96efb552603541279a467ff577faaba995 (diff) | |
download | barebox-a06513273fc18c16b5081ddd80ce14b7de37cf6e.tar.gz barebox-a06513273fc18c16b5081ddd80ce14b7de37cf6e.tar.xz |
Merge branch 'for-next/dts'
Diffstat (limited to 'dts/Bindings/net')
-rw-r--r-- | dts/Bindings/net/mediatek-net.txt | 2 | ||||
-rw-r--r-- | dts/Bindings/net/phy.txt | 5 | ||||
-rw-r--r-- | dts/Bindings/net/ti,dp83867.txt | 6 |
3 files changed, 8 insertions, 5 deletions
diff --git a/dts/Bindings/net/mediatek-net.txt b/dts/Bindings/net/mediatek-net.txt index c010fafc66..c7194e87d5 100644 --- a/dts/Bindings/net/mediatek-net.txt +++ b/dts/Bindings/net/mediatek-net.txt @@ -7,7 +7,7 @@ have dual GMAC each represented by a child node.. * Ethernet controller node Required properties: -- compatible: Should be "mediatek,mt7623-eth" +- compatible: Should be "mediatek,mt2701-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. diff --git a/dts/Bindings/net/phy.txt b/dts/Bindings/net/phy.txt index ff1bc4b1bb..fb5056b226 100644 --- a/dts/Bindings/net/phy.txt +++ b/dts/Bindings/net/phy.txt @@ -19,8 +19,9 @@ Optional Properties: specifications. If neither of these are specified, the default is to assume clause 22. - If the phy's identifier is known then the list may contain an entry - of the form: "ethernet-phy-idAAAA.BBBB" where + If the PHY reports an incorrect ID (or none at all) then the + "compatible" list may contain an entry with the correct PHY ID in the + form: "ethernet-phy-idAAAA.BBBB" where AAAA - The value of the 16 bit Phy Identifier 1 register as 4 hex digits. This is the chip vendor OUI bits 3:18 BBBB - The value of the 16 bit Phy Identifier 2 register as diff --git a/dts/Bindings/net/ti,dp83867.txt b/dts/Bindings/net/ti,dp83867.txt index 85bf945b89..afe9630a5e 100644 --- a/dts/Bindings/net/ti,dp83867.txt +++ b/dts/Bindings/net/ti,dp83867.txt @@ -3,9 +3,11 @@ Required properties: - reg - The ID number for the phy, usually a small integer - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values |