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authorSascha Hauer <s.hauer@pengutronix.de>2016-09-29 14:38:07 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-09-29 14:38:07 +0200
commitd9a15385467936649b6c2cfeb7ab377002ddce0f (patch)
tree39175107fc884a29fbba83f47d104f493833fe19 /dts/Bindings/net
parentbfe946c9593513b0ad1b440bcd997b263487b945 (diff)
downloadbarebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.gz
barebox-d9a15385467936649b6c2cfeb7ab377002ddce0f.tar.xz
dts: update to v4.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/net')
-rw-r--r--dts/Bindings/net/apm-xgene-enet.txt4
-rw-r--r--dts/Bindings/net/apm-xgene-mdio.txt37
-rw-r--r--dts/Bindings/net/brcm,mdio-mux-iproc.txt59
-rw-r--r--dts/Bindings/net/can/rcar_canfd.txt96
-rw-r--r--dts/Bindings/net/cavium-pip.txt6
-rw-r--r--dts/Bindings/net/cirrus,cs89x0.txt13
-rw-r--r--dts/Bindings/net/cpsw.txt1
-rw-r--r--dts/Bindings/net/davinci-mdio.txt5
-rw-r--r--dts/Bindings/net/dsa/b53.txt97
-rw-r--r--dts/Bindings/net/dsa/dsa.txt280
-rw-r--r--dts/Bindings/net/fsl-fec.txt3
-rw-r--r--dts/Bindings/net/hisilicon-femac-mdio.txt22
-rw-r--r--dts/Bindings/net/hisilicon-femac.txt39
-rw-r--r--dts/Bindings/net/keystone-netcp.txt2
-rw-r--r--dts/Bindings/net/mdio-mux.txt3
-rw-r--r--dts/Bindings/net/micrel.txt10
-rw-r--r--dts/Bindings/net/rockchip-dwmac.txt3
-rw-r--r--dts/Bindings/net/socfpga-dwmac.txt19
-rw-r--r--dts/Bindings/net/stmmac.txt3
-rw-r--r--dts/Bindings/net/wireless/ti,wlcore,spi.txt41
20 files changed, 724 insertions, 19 deletions
diff --git a/dts/Bindings/net/apm-xgene-enet.txt b/dts/Bindings/net/apm-xgene-enet.txt
index 05f705e32a..e41b2d59ca 100644
--- a/dts/Bindings/net/apm-xgene-enet.txt
+++ b/dts/Bindings/net/apm-xgene-enet.txt
@@ -59,8 +59,8 @@ Example:
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
- <0x0 0X17030000 0x0 0X400>,
- <0x0 0X10000000 0x0 0X200>;
+ <0x0 0x17030000 0x0 0x400>,
+ <0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
port-id = <0>;
diff --git a/dts/Bindings/net/apm-xgene-mdio.txt b/dts/Bindings/net/apm-xgene-mdio.txt
new file mode 100644
index 0000000000..78722d74ce
--- /dev/null
+++ b/dts/Bindings/net/apm-xgene-mdio.txt
@@ -0,0 +1,37 @@
+APM X-Gene SoC MDIO node
+
+MDIO node is defined to describe on-chip MDIO controller.
+
+Required properties:
+ - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+ - reg: Address and length of the register set
+ - clocks: Reference to the clock entry
+
+For the phys on the mdio bus, there must be a node with the following fields:
+ - compatible: PHY identifier. Please refer ./phy.txt for the format.
+ - reg: The ID number for the phy.
+
+Example:
+
+ mdio: mdio@17020000 {
+ compatible = "apm,xgene-mdio-rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x17020000 0x0 0xd100>;
+ clocks = <&menetclk 0>;
+ };
+
+ /* Board-specific peripheral configurations */
+ &mdio {
+ menetphy: phy@3 {
+ reg = <0x3>;
+ };
+ sgenet0phy: phy@4 {
+ reg = <0x4>;
+ };
+ sgenet1phy: phy@5 {
+ reg = <0x5>;
+ };
+ };
diff --git a/dts/Bindings/net/brcm,mdio-mux-iproc.txt b/dts/Bindings/net/brcm,mdio-mux-iproc.txt
new file mode 100644
index 0000000000..dfe287a5d6
--- /dev/null
+++ b/dts/Bindings/net/brcm,mdio-mux-iproc.txt
@@ -0,0 +1,59 @@
+Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
+
+This MDIO bus multiplexer defines buses that could be internal as well as
+external to SoCs and could accept MDIO transaction compatible to C-22 or
+C-45 Clause. When child bus is selected, one needs to select these two
+properties as well to generate desired MDIO transaction on appropriate bus.
+
+Required properties in addition to the generic multiplexer properties:
+
+MDIO multiplexer node:
+- compatible: brcm,mdio-mux-iproc.
+
+Every non-ethernet PHY requires a compatible so that it could be probed based
+on this compatible string.
+
+Additional information regarding generic multiplexer properties can be found
+at- Documentation/devicetree/bindings/net/mdio-mux.txt
+
+
+for example:
+ mdio_mux_iproc: mdio-mux@6602023c {
+ compatible = "brcm,mdio-mux-iproc";
+ reg = <0x6602023c 0x14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy0: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+ };
+
+ mdio@7 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pci_phy1: pci-phy@0 {
+ compatible = "brcm,ns2-pcie-phy";
+ reg = <0x0>;
+ #phy-cells = <0>;
+ };
+ };
+ mdio@10 {
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gphy0: eth-phy@10 {
+ reg = <0x10>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/can/rcar_canfd.txt b/dts/Bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000000..22a6f10bab
--- /dev/null
+++ b/dts/Bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,96 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+ - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+ - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first, followed by the
+ family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Optional property:
+The controller can operate in either CAN FD only mode (default) or
+Classical CAN only mode. The mode is global to both the channels. In order to
+enable the later, define the following optional property.
+ - renesas,no-can-fd: puts the controller in Classical CAN only mode.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a7795-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
+
+&canfd {
+ pinctrl-0 = <&canfd1_pins>;
+ pinctrl-names = "default";
+ renesas,no-can-fd;
+ status = "okay";
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+ pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+};
diff --git a/dts/Bindings/net/cavium-pip.txt b/dts/Bindings/net/cavium-pip.txt
index 7dbd158810..e3b8fe7176 100644
--- a/dts/Bindings/net/cavium-pip.txt
+++ b/dts/Bindings/net/cavium-pip.txt
@@ -37,6 +37,12 @@ Properties for PIP port which is a child the PIP interface:
- phy-handle: Optional, see ethernet.txt file in the same directory.
+- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
+ Value range is 1-31, and mapping to the actual delay varies depending on HW.
+
+- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
+ Value range is 1-31, and mapping to the actual delay varies depending on HW.
+
Example:
pip@11800a0000000 {
diff --git a/dts/Bindings/net/cirrus,cs89x0.txt b/dts/Bindings/net/cirrus,cs89x0.txt
new file mode 100644
index 0000000000..c070076bac
--- /dev/null
+++ b/dts/Bindings/net/cirrus,cs89x0.txt
@@ -0,0 +1,13 @@
+* Cirrus Logic CS8900/CS8920 Network Controller
+
+Required properties:
+- compatible : Should be "cirrus,cs8900" or "cirrus,cs8920".
+- reg : Address and length of the IO space.
+- interrupts : Should contain the controller interrupt line.
+
+Examples:
+ eth0: eth@10000000 {
+ compatible = "cirrus,cs8900";
+ reg = <0x10000000 0x400>;
+ interrupts = <10>;
+ };
diff --git a/dts/Bindings/net/cpsw.txt b/dts/Bindings/net/cpsw.txt
index 0ae06491b4..5ad439f301 100644
--- a/dts/Bindings/net/cpsw.txt
+++ b/dts/Bindings/net/cpsw.txt
@@ -15,7 +15,6 @@ Required properties:
- cpdma_channels : Specifies number of channels in CPDMA
- ale_entries : Specifies No of entries ALE can hold
- bd_ram_size : Specifies internal descriptor RAM size
-- rx_descs : Specifies number of Rx descriptors
- mac_control : Specifies Default MAC control register content
for the specific platform
- slaves : Specifies number for slaves
diff --git a/dts/Bindings/net/davinci-mdio.txt b/dts/Bindings/net/davinci-mdio.txt
index 0369e25aab..621156ca4f 100644
--- a/dts/Bindings/net/davinci-mdio.txt
+++ b/dts/Bindings/net/davinci-mdio.txt
@@ -2,7 +2,10 @@ TI SoC Davinci/Keystone2 MDIO Controller Device Tree Bindings
---------------------------------------------------
Required properties:
-- compatible : Should be "ti,davinci_mdio" or "ti,keystone_mdio"
+- compatible : Should be "ti,davinci_mdio"
+ and "ti,keystone_mdio" for Keystone 2 SoCs
+ and "ti,cpsw-mdio" for am335x, am472x, am57xx/dra7, dm814x SoCs
+ and "ti,am4372-mdio" for am472x SoC
- reg : physical base address and size of the davinci mdio
registers map
- bus_freq : Mdio Bus frequency
diff --git a/dts/Bindings/net/dsa/b53.txt b/dts/Bindings/net/dsa/b53.txt
new file mode 100644
index 0000000000..d6c6e41648
--- /dev/null
+++ b/dts/Bindings/net/dsa/b53.txt
@@ -0,0 +1,97 @@
+Broadcom BCM53xx Ethernet switches
+==================================
+
+Required properties:
+
+- compatible: For external switch chips, compatible string must be exactly one
+ of: "brcm,bcm5325"
+ "brcm,bcm53115"
+ "brcm,bcm53125"
+ "brcm,bcm53128"
+ "brcm,bcm5365"
+ "brcm,bcm5395"
+ "brcm,bcm5397"
+ "brcm,bcm5398"
+
+ For the BCM5310x SoCs with an integrated switch, must be one of:
+ "brcm,bcm53010-srab"
+ "brcm,bcm53011-srab"
+ "brcm,bcm53012-srab"
+ "brcm,bcm53018-srab"
+ "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
+
+ For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of:
+ "brcm,bcm58522-srab"
+ "brcm,bcm58523-srab"
+ "brcm,bcm58525-srab"
+ "brcm,bcm58622-srab"
+ "brcm,bcm58623-srab"
+ "brcm,bcm58625-srab"
+ "brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string
+
+ For the BCM63xx/33xx SoCs with an integrated switch, must be one of:
+ "brcm,bcm3384-switch"
+ "brcm,bcm6328-switch"
+ "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
+
+See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
+required and optional properties.
+
+Examples:
+
+Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
+
+ eth0: ethernet@10001000 {
+ compatible = "brcm,unimac";
+ reg = <0x10001000 0x1000>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+
+ mdio0: mdio@10000000 {
+ compatible = "brcm,unimac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0: ethernet-switch@30 {
+ compatible = "brcm,bcm53125";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ port0@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port1@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port5@5 {
+ reg = <5>;
+ label = "cable-modem";
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ phy-mode = "rgmii-txid";
+ };
+
+ port8@8 {
+ reg = <8>;
+ label = "cpu";
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ phy-mode = "rgmii-txid";
+ ethernet = <&eth0>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/net/dsa/dsa.txt b/dts/Bindings/net/dsa/dsa.txt
index 9f4807f90c..a4a570fb24 100644
--- a/dts/Bindings/net/dsa/dsa.txt
+++ b/dts/Bindings/net/dsa/dsa.txt
@@ -1,5 +1,279 @@
-Marvell Distributed Switch Architecture Device Tree Bindings
-------------------------------------------------------------
+Distributed Switch Architecture Device Tree Bindings
+----------------------------------------------------
+
+Two bindings exist, one of which has been deprecated due to
+limitations.
+
+Current Binding
+---------------
+
+Switches are true Linux devices and can be probes by any means. Once
+probed, they register to the DSA framework, passing a node
+pointer. This node is expected to fulfil the following binding, and
+may contain additional properties as required by the device it is
+embedded within.
+
+Required properties:
+
+- ports : A container for child nodes representing switch ports.
+
+Optional properties:
+
+- dsa,member : A two element list indicates which DSA cluster, and position
+ within the cluster a switch takes. <0 0> is cluster 0,
+ switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
+ switch 0. A switch not part of any cluster (single device
+ hanging off a CPU port) must not specify this property
+
+The ports container has the following properties
+
+Required properties:
+
+- #address-cells : Must be 1
+- #size-cells : Must be 0
+
+Each port children node must have the following mandatory properties:
+- reg : Describes the port address in the switch
+- label : Describes the label associated with this port, which
+ will become the netdev name. Special labels are
+ "cpu" to indicate a CPU port and "dsa" to
+ indicate an uplink/downlink port between switches in
+ the cluster.
+
+A port labelled "dsa" has the following mandatory property:
+
+- link : Should be a list of phandles to other switch's DSA
+ port. This port is used as the outgoing port
+ towards the phandle ports. The full routing
+ information must be given, not just the one hop
+ routes to neighbouring switches.
+
+A port labelled "cpu" has the following mandatory property:
+
+- ethernet : Should be a phandle to a valid Ethernet device node.
+ This host device is what the switch port is
+ connected to.
+
+Port child nodes may also contain the following optional standardised
+properties, described in binding documents:
+
+- phy-handle : Phandle to a PHY on an MDIO bus. See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+- phy-mode : See
+ Documentation/devicetree/bindings/net/ethernet.txt
+ for details.
+
+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+
+Example
+
+The following example shows three switches on three MDIO busses,
+linked into one DSA cluster.
+
+&mdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0: switch0@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ switch0port5: port@5 {
+ reg = <5>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch1port6
+ &switch2port9>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch1: switch1@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ phy-handle = <&switch1phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ phy-handle = <&switch1phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan5";
+ phy-handle = <&switch1phy2>;
+ };
+
+ switch1port5: port@5 {
+ reg = <5>;
+ label = "dsa";
+ link = <&switch2port9>;
+ phy-mode = "rgmii-txid";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch1port6: port@6 {
+ reg = <6>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ switch1phy0: switch1phy0@0 {
+ reg = <0>;
+ };
+ switch1phy1: switch1phy0@1 {
+ reg = <1>;
+ };
+ switch1phy2: switch1phy0@2 {
+ reg = <2>;
+ };
+ };
+ };
+};
+
+&mdio4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch2: switch2@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dsa,member = <0 2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan6";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan7";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan8";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "optical3";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio6 2
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "optical4";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ link-gpios = <&gpio6 3
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ switch2port9: port@9 {
+ reg = <9>;
+ label = "dsa";
+ phy-mode = "rgmii-txid";
+ link = <&switch1port5
+ &switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+Deprecated Binding
+------------------
+
+The deprecated binding makes use of a platform device to represent the
+switches. The switches themselves are not Linux devices, and make use
+of an MDIO bus for management.
Required properties:
- compatible : Should be "marvell,dsa"
@@ -43,7 +317,7 @@ Each port children node must have the following mandatory properties:
Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.
-Optionnal property:
+Optional property:
- link : Should be a list of phandles to another switch's DSA port.
This property is only used when switches are being
chained/cascaded together. This port is used as outgoing port
diff --git a/dts/Bindings/net/fsl-fec.txt b/dts/Bindings/net/fsl-fec.txt
index b037a9d78d..a1e3693cca 100644
--- a/dts/Bindings/net/fsl-fec.txt
+++ b/dts/Bindings/net/fsl-fec.txt
@@ -27,6 +27,9 @@ Optional properties:
number to 1.
- fsl,magic-packet : If present, indicates that the hardware supports waking
up via magic packet.
+- fsl,err006687-workaround-present: If present indicates that the system has
+ the hardware workaround for ERR006687 applied and does not need a software
+ workaround.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
diff --git a/dts/Bindings/net/hisilicon-femac-mdio.txt b/dts/Bindings/net/hisilicon-femac-mdio.txt
new file mode 100644
index 0000000000..23a39a309d
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-femac-mdio.txt
@@ -0,0 +1,22 @@
+Hisilicon Fast Ethernet MDIO Controller interface
+
+Required properties:
+- compatible: should be "hisilicon,hisi-femac-mdio".
+- reg: address and length of the register set for the device.
+- clocks: A phandle to the reference clock for this device.
+
+- PHY subnode: inherits from phy binding [1]
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+mdio: mdio@10091100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10091100 0x10>;
+ clocks = <&crg HI3516CV300_MDIO_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@1 {
+ reg = <1>;
+ };
+};
diff --git a/dts/Bindings/net/hisilicon-femac.txt b/dts/Bindings/net/hisilicon-femac.txt
new file mode 100644
index 0000000000..d11af5ecac
--- /dev/null
+++ b/dts/Bindings/net/hisilicon-femac.txt
@@ -0,0 +1,39 @@
+Hisilicon Fast Ethernet MAC controller
+
+Required properties:
+- compatible: should contain one of the following version strings:
+ * "hisilicon,hisi-femac-v1"
+ * "hisilicon,hisi-femac-v2"
+ and the soc string "hisilicon,hi3516cv300-femac".
+- reg: specifies base physical address(s) and size of the device registers.
+ The first region is the MAC core register base and size.
+ The second region is the global MAC control register.
+- interrupts: should contain the MAC interrupt.
+- clocks: A phandle to the MAC main clock.
+- resets: should contain the phandle to the MAC reset signal(required) and
+ the PHY reset signal(optional).
+- reset-names: should contain the reset signal name "mac"(required)
+ and "phy"(optional).
+- mac-address: see ethernet.txt [1].
+- phy-mode: see ethernet.txt [1].
+- phy-handle: see ethernet.txt [1].
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
+
+[1] Documentation/devicetree/bindings/net/ethernet.txt
+
+Example:
+ hisi_femac: ethernet@10090000 {
+ compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
+ reg = <0x10090000 0x1000>,<0x10091300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3518EV200_ETH_CLK>;
+ resets = <&crg 0xec 0>,<&crg 0xec 3>;
+ reset-names = "mac","phy";
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "mii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays-us = <10000 20000 20000>;
+ };
diff --git a/dts/Bindings/net/keystone-netcp.txt b/dts/Bindings/net/keystone-netcp.txt
index b30ab6b5cb..04ba1dc34f 100644
--- a/dts/Bindings/net/keystone-netcp.txt
+++ b/dts/Bindings/net/keystone-netcp.txt
@@ -2,7 +2,7 @@ This document describes the device tree bindings associated with the
keystone network coprocessor(NetCP) driver support.
The network coprocessor (NetCP) is a hardware accelerator that processes
-Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsytem with a ethernet
+Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accelerator (PA) module to perform packet classification operations such as
header matching, and packet modification operations such as checksum
diff --git a/dts/Bindings/net/mdio-mux.txt b/dts/Bindings/net/mdio-mux.txt
index 491f5bd552..f58571f365 100644
--- a/dts/Bindings/net/mdio-mux.txt
+++ b/dts/Bindings/net/mdio-mux.txt
@@ -5,11 +5,12 @@ numbered uniquely in a device dependent manner. The nodes for an MDIO
bus multiplexer/switch will have one child node for each child bus.
Required properties:
-- mdio-parent-bus : phandle to the parent MDIO bus.
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties:
+- mdio-parent-bus : phandle to the parent MDIO bus.
+
- Other properties specific to the multiplexer/switch hardware.
Required properties for child nodes:
diff --git a/dts/Bindings/net/micrel.txt b/dts/Bindings/net/micrel.txt
index 87496a8c64..8d157f0295 100644
--- a/dts/Bindings/net/micrel.txt
+++ b/dts/Bindings/net/micrel.txt
@@ -35,3 +35,13 @@ Optional properties:
supported clocks:
- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
input clock. Used to determine the XI input clock.
+
+ - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
+
+ Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
+ by the FXEN boot strapping pin. It can't be determined from the PHY
+ registers whether the PHY is in fiber mode, so this boolean device tree
+ property can be used to describe it.
+
+ In fiber mode, auto-negotiation is disabled and the PHY can only work in
+ 100base-fx (full and half duplex) modes.
diff --git a/dts/Bindings/net/rockchip-dwmac.txt b/dts/Bindings/net/rockchip-dwmac.txt
index 93eac7ce14..cccd945fc4 100644
--- a/dts/Bindings/net/rockchip-dwmac.txt
+++ b/dts/Bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,8 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
The device node has following properties.
Required properties:
- - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac"
+ - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
+ "rockchip,rk3368-gmac"
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
diff --git a/dts/Bindings/net/socfpga-dwmac.txt b/dts/Bindings/net/socfpga-dwmac.txt
index 72d82d6843..2e68a3cd85 100644
--- a/dts/Bindings/net/socfpga-dwmac.txt
+++ b/dts/Bindings/net/socfpga-dwmac.txt
@@ -17,9 +17,26 @@ Required properties:
Optional properties:
altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
DWMAC controller is connected emac splitter.
+phy-mode: The phy mode the ethernet operates in
+altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
+
+This device node has additional phandle dependency, the sgmii converter:
+
+Required properties:
+ - compatible : Should be altr,gmii-to-sgmii-2.0
+ - reg-names : Should be "eth_tse_control_port"
Example:
+gmii_to_sgmii_converter: phy@0x100000240 {
+ compatible = "altr,gmii-to-sgmii-2.0";
+ reg = <0x00000001 0x00000240 0x00000008>,
+ <0x00000001 0x00000200 0x00000040>;
+ reg-names = "eth_tse_control_port";
+ clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
+ clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+};
+
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -30,4 +47,6 @@ gmac0: ethernet@ff700000 {
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
+ phy-mode = "sgmii";
+ altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
};
diff --git a/dts/Bindings/net/stmmac.txt b/dts/Bindings/net/stmmac.txt
index 95816c5fc5..41b49e6075 100644
--- a/dts/Bindings/net/stmmac.txt
+++ b/dts/Bindings/net/stmmac.txt
@@ -47,6 +47,9 @@ Optional properties:
supported by this device instance
- snps,perfect-filter-entries: Number of perfect filter entries supported
by this device instance
+- snps,ps-speed: port selection speed that can be passed to the core when
+ PCS is supported. For example, this is used in case of SGMII
+ and MAC2MAC connection.
- AXI BUS Mode parameters: below the list of all the parameters to program the
AXI register inside the DMA module:
- snps,lpi_en: enable Low Power Interface
diff --git a/dts/Bindings/net/wireless/ti,wlcore,spi.txt b/dts/Bindings/net/wireless/ti,wlcore,spi.txt
index 9180724e18..8f9ced076f 100644
--- a/dts/Bindings/net/wireless/ti,wlcore,spi.txt
+++ b/dts/Bindings/net/wireless/ti,wlcore,spi.txt
@@ -1,19 +1,30 @@
-* Texas Instruments wl1271 wireless lan controller
+* Texas Instruments wl12xx/wl18xx wireless lan controller
-The wl1271 chip can be connected via SPI or via SDIO. This
+The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This
document describes the binding for the SPI connected chip.
Required properties:
-- compatible : Should be "ti,wl1271"
+- compatible : Should be one of the following:
+ * "ti,wl1271"
+ * "ti,wl1273"
+ * "ti,wl1281"
+ * "ti,wl1283"
+ * "ti,wl1801"
+ * "ti,wl1805"
+ * "ti,wl1807"
+ * "ti,wl1831"
+ * "ti,wl1835"
+ * "ti,wl1837"
- reg : Chip select address of device
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
-- ref-clock-frequency : Reference clock frequency
- interrupt-parent, interrupts :
Should contain parameters for 1 interrupt line.
Interrupt parameters: parent, line number, type.
-- vwlan-supply : Point the node of the regulator that powers/enable the wl1271 chip
+- vwlan-supply : Point the node of the regulator that powers/enable the
+ wl12xx/wl18xx chip
Optional properties:
+- ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
- clock-xtal : boolean, clock is generated from XTAL
- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -21,16 +32,28 @@ Optional properties:
Examples:
+For wl12xx family:
&spi1 {
- wl1271@1 {
+ wlcore: wlcore@1 {
compatible = "ti,wl1271";
-
reg = <1>;
spi-max-frequency = <48000000>;
- clock-xtal;
- ref-clock-frequency = <38400000>;
interrupt-parent = <&gpio3>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
vwlan-supply = <&vwlan_fixed>;
+ clock-xtal;
+ ref-clock-frequency = <38400000>;
+ };
+};
+
+For wl18xx family:
+&spi0 {
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1835";
+ reg = <0>;
+ spi-max-frequency = <48000000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <27 IRQ_TYPE_EDGE_RISING>;
+ vwlan-supply = <&vwlan_fixed>;
};
};