diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-27 11:22:53 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-28 15:31:59 +0100 |
commit | 5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08 (patch) | |
tree | 0634f20e5f75f3d44242af47eebd9ea1ce0163f6 /dts/Bindings/pci | |
parent | db35548372eaee835fbf9bae68c08362ba59d49d (diff) | |
download | barebox-5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08.tar.gz barebox-5f3e773ca4830daf71c7b5eee0c6b1dfe4d09c08.tar.xz |
dts: update to v5.17-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pci')
-rw-r--r-- | dts/Bindings/pci/apple,pcie.yaml | 28 | ||||
-rw-r--r-- | dts/Bindings/pci/brcm,iproc-pcie.txt | 133 | ||||
-rw-r--r-- | dts/Bindings/pci/brcm,iproc-pcie.yaml | 184 | ||||
-rw-r--r-- | dts/Bindings/pci/brcm,stb-pcie.yaml | 30 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns,cdns-pcie-ep.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns-pcie-ep.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/pci/fsl,imx6q-pcie.yaml | 6 | ||||
-rw-r--r-- | dts/Bindings/pci/hisilicon,kirin-pcie.yaml | 13 | ||||
-rw-r--r-- | dts/Bindings/pci/mediatek,mt7621-pcie.yaml | 3 | ||||
-rw-r--r-- | dts/Bindings/pci/mediatek-pcie-gen3.yaml | 4 | ||||
-rw-r--r-- | dts/Bindings/pci/microchip,pcie-host.yaml | 18 | ||||
-rw-r--r-- | dts/Bindings/pci/sifive,fu740-pcie.yaml | 5 | ||||
-rw-r--r-- | dts/Bindings/pci/snps,dw-pcie-ep.yaml | 6 | ||||
-rw-r--r-- | dts/Bindings/pci/snps,dw-pcie.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/pci/ti,am65-pci-ep.yaml | 10 | ||||
-rw-r--r-- | dts/Bindings/pci/ti,am65-pci-host.yaml | 20 | ||||
-rw-r--r-- | dts/Bindings/pci/ti,j721e-pci-host.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/pci/xilinx-versal-cpm.yaml | 1 |
19 files changed, 306 insertions, 163 deletions
diff --git a/dts/Bindings/pci/apple,pcie.yaml b/dts/Bindings/pci/apple,pcie.yaml index ef1d424ec2..7f01e15fc8 100644 --- a/dts/Bindings/pci/apple,pcie.yaml +++ b/dts/Bindings/pci/apple,pcie.yaml @@ -28,19 +28,17 @@ description: | distributed over the root ports as the OS sees fit by programming the PCIe controller's port registers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/interrupt-controller/msi-controller.yaml# - properties: compatible: items: - - const: apple,t8103-pcie + - enum: + - apple,t8103-pcie + - apple,t6000-pcie - const: apple,pcie reg: minItems: 3 - maxItems: 5 + maxItems: 6 reg-names: minItems: 3 @@ -50,6 +48,7 @@ properties: - const: port0 - const: port1 - const: port2 + - const: port3 ranges: minItems: 2 @@ -59,7 +58,7 @@ properties: description: Interrupt specifiers, one for each root port. minItems: 1 - maxItems: 3 + maxItems: 4 msi-parent: true @@ -81,6 +80,21 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8103-pcie + then: + properties: + reg: + maxItems: 5 + interrupts: + maxItems: 3 + examples: - | #include <dt-bindings/interrupt-controller/apple-aic.h> diff --git a/dts/Bindings/pci/brcm,iproc-pcie.txt b/dts/Bindings/pci/brcm,iproc-pcie.txt deleted file mode 100644 index df065aa53a..0000000000 --- a/dts/Bindings/pci/brcm,iproc-pcie.txt +++ /dev/null @@ -1,133 +0,0 @@ -* Broadcom iProc PCIe controller with the platform bus interface - -Required properties: -- compatible: - "brcm,iproc-pcie" for the first generation of PAXB based controller, -used in SoCs including NSP, Cygnus, NS2, and Pegasus - "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based -controllers, used in Stingray - "brcm,iproc-pcie-paxc" for the first generation of PAXC based -controller, used in NS2 - "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -controller, used in Stingray - PAXB-based root complex is used for external endpoint devices. PAXC-based -root complex is connected to emulated endpoint devices internal to the ASIC -- reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers -- linux,pci-domain: PCI domain ID. Should be unique for each host controller -- bus-range: PCI bus numbers covered -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions - -Optional properties: -- phys: phandle of the PCIe PHY device -- phy-names: must be "pcie-phy" -- dma-coherent: present if DMA operations are coherent -- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done - by the ASIC after power on reset. In this case, SW is required to configure -the mapping, based on inbound memory regions specified by this property. - -- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -by the ASIC after power on reset. In this case, SW needs to configure it - -If the brcm,pcie-ob property is present, the following properties become -effective: - -Required: -- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -address used by the iProc PCIe core (not the PCIe address) - -MSI support (optional): - -For older platforms without MSI integrated in the GIC, iProc PCIe core provides -an event queue based MSI support. The iProc MSI uses host memories to store -MSI posted writes in the event queues - -On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used - -- msi-map: Maps a Requester ID to an MSI controller and associated MSI -sideband data - -- msi-parent: Link to the device node of the MSI controller, used when no MSI -sideband data is passed between the iProc PCIe controller and the MSI -controller - -Refer to the following binding documents for more detailed description on -the use of 'msi-map' and 'msi-parent': - Documentation/devicetree/bindings/pci/pci-msi.txt - Documentation/devicetree/bindings/interrupt-controller/msi.txt - -When the iProc event queue based MSI is used, one needs to define the -following properties in the MSI device node: -- compatible: Must be "brcm,iproc-msi" -- msi-controller: claims itself as an MSI controller -- interrupts: List of interrupt IDs from its parent interrupt device - -Optional properties: -- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -require the interrupt enable registers to be set explicitly to enable MSI - -Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18012000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x28000000 0 0x00010000 - 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; - - brcm,pcie-ob; - brcm,pcie-ob-axi-offset = <0x00000000>; - - msi-parent = <&msi0>; - - /* iProc event queue based MSI */ - msi0: msi@18012000 { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, - <GIC_SPI 97 IRQ_TYPE_NONE>, - <GIC_SPI 98 IRQ_TYPE_NONE>, - <GIC_SPI 99 IRQ_TYPE_NONE>, - }; - }; - - pcie1: pcie@18013000 { - compatible = "brcm,iproc-pcie"; - reg = <0x18013000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x48000000 0 0x00010000 - 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; - - phys = <&phy 1 6>; - phy-names = "pcie-phy"; - }; diff --git a/dts/Bindings/pci/brcm,iproc-pcie.yaml b/dts/Bindings/pci/brcm,iproc-pcie.yaml new file mode 100644 index 0000000000..0972868735 --- /dev/null +++ b/dts/Bindings/pci/brcm,iproc-pcie.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PCIe controller with the platform bus interface + +maintainers: + - Ray Jui <ray.jui@broadcom.com> + - Scott Branden <scott.branden@broadcom.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + # for the first generation of PAXB based controller, used in SoCs + # including NSP, Cygnus, NS2, and Pegasus + - brcm,iproc-pcie + # for the second generation of PAXB-based controllers, used in + # Stingray + - brcm,iproc-pcie-paxb-v2 + # For the first generation of PAXC based controller, used in NS2 + - brcm,iproc-pcie-paxc + # For the second generation of PAXC based controller, used in Stingray + - brcm,iproc-pcie-paxc-v2 + + reg: + maxItems: 1 + description: > + Base address and length of the PCIe controller I/O register space + + interrupt-map: true + + interrupt-map-mask: true + + "#interrupt-cells": + const: 1 + + ranges: + minItems: 1 + maxItems: 2 + description: > + Ranges for the PCI memory and I/O regions + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + bus-range: true + + dma-coherent: true + + "#address-cells": true + + "#size-cells": true + + device_type: true + + brcm,pcie-ob: + type: boolean + description: > + Some iProc SoCs do not have the outbound address mapping done by the + ASIC after power on reset. In this case, SW needs to configure it + + brcm,pcie-ob-axi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The offset from the AXI address to the internal address used by the + iProc PCIe core (not the PCIe address) + + msi: + type: object + properties: + compatible: + items: + - const: brcm,iproc-msi + + msi-parent: true + + msi-controller: true + + brcm,pcie-msi-inten: + type: boolean + description: > + Needs to be present for some older iProc platforms that require the + interrupt enable registers to be set explicitly to enable MSI + +dependencies: + brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"] + brcm,pcie-msi-inten: [msi-controller] + +required: + - compatible + - reg + - ranges + +if: + properties: + compatible: + contains: + enum: + - brcm,iproc-pcie +then: + required: + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <1>; + #size-cells = <1>; + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, + <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; + + phys = <&phy 0 5>; + phy-names = "pcie-phy"; + + brcm,pcie-ob; + brcm,pcie-ob-axi-offset = <0x00000000>; + + msi-parent = <&msi0>; + + /* iProc event queue based MSI */ + msi0: msi { + compatible = "brcm,iproc-msi"; + msi-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, + <GIC_SPI 97 IRQ_TYPE_NONE>, + <GIC_SPI 98 IRQ_TYPE_NONE>, + <GIC_SPI 99 IRQ_TYPE_NONE>; + }; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; + + phys = <&phy 1 6>; + phy-names = "pcie-phy"; + }; + }; diff --git a/dts/Bindings/pci/brcm,stb-pcie.yaml b/dts/Bindings/pci/brcm,stb-pcie.yaml index 1fe102743f..0f064e4222 100644 --- a/dts/Bindings/pci/brcm,stb-pcie.yaml +++ b/dts/Bindings/pci/brcm,stb-pcie.yaml @@ -19,6 +19,8 @@ properties: - brcm,bcm7278-pcie # Broadcom 7278 Arm - brcm,bcm7216-pcie # Broadcom 7216 Arm - brcm,bcm7445-pcie # Broadcom 7445 Arm + - brcm,bcm7425-pcie # Broadcom 7425 MIPs + - brcm,bcm7435-pcie # Broadcom 7435 MIPs reg: maxItems: 1 @@ -76,6 +78,7 @@ properties: maxItems: 3 required: + - compatible - reg - ranges - dma-ranges @@ -143,11 +146,15 @@ examples: #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pcie", "msi"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie0>; msi-controller; ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; @@ -155,5 +162,24 @@ examples: <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + + /* PCIe bridge, Root Port */ + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + vpcie3v3-supply = <&vreg7>; + ranges; + + /* PCIe endpoint */ + pci-ep@0,0 { + assigned-addresses = + <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pci14e4,1688"; + }; + }; }; }; diff --git a/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml b/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml index 651eee8898..e6ef1012a5 100644 --- a/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml @@ -11,7 +11,6 @@ maintainers: allOf: - $ref: "cdns-pcie-ep.yaml#" - - $ref: "pci-ep.yaml#" properties: compatible: diff --git a/dts/Bindings/pci/cdns-pcie-ep.yaml b/dts/Bindings/pci/cdns-pcie-ep.yaml index 21e8a88490..baeafda36e 100644 --- a/dts/Bindings/pci/cdns-pcie-ep.yaml +++ b/dts/Bindings/pci/cdns-pcie-ep.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: "cdns-pcie.yaml#" + - $ref: "pci-ep.yaml#" properties: cdns,max-outbound-regions: diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.yaml b/dts/Bindings/pci/fsl,imx6q-pcie.yaml index acea1cd444..643a6333b0 100644 --- a/dts/Bindings/pci/fsl,imx6q-pcie.yaml +++ b/dts/Bindings/pci/fsl,imx6q-pcie.yaml @@ -127,6 +127,12 @@ properties: enum: [1, 2, 3, 4] default: 1 + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset diff --git a/dts/Bindings/pci/hisilicon,kirin-pcie.yaml b/dts/Bindings/pci/hisilicon,kirin-pcie.yaml index cbee878025..c9f04999c9 100644 --- a/dts/Bindings/pci/hisilicon,kirin-pcie.yaml +++ b/dts/Bindings/pci/hisilicon,kirin-pcie.yaml @@ -37,6 +37,19 @@ properties: minItems: 3 maxItems: 4 + clocks: true + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_aux + - const: pcie_apb_phy + - const: pcie_apb_sys + - const: pcie_aclk + + phys: + maxItems: 1 + hisilicon,clken-gpios: description: | Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and diff --git a/dts/Bindings/pci/mediatek,mt7621-pcie.yaml b/dts/Bindings/pci/mediatek,mt7621-pcie.yaml index 044fa967bc..d60f43fd9c 100644 --- a/dts/Bindings/pci/mediatek,mt7621-pcie.yaml +++ b/dts/Bindings/pci/mediatek,mt7621-pcie.yaml @@ -45,6 +45,9 @@ patternProperties: phys: maxItems: 1 + phy-names: + pattern: '^pcie-phy[0-2]$' + required: - "#interrupt-cells" - interrupt-map-mask diff --git a/dts/Bindings/pci/mediatek-pcie-gen3.yaml b/dts/Bindings/pci/mediatek-pcie-gen3.yaml index 742206dbd9..0499b94627 100644 --- a/dts/Bindings/pci/mediatek-pcie-gen3.yaml +++ b/dts/Bindings/pci/mediatek-pcie-gen3.yaml @@ -95,6 +95,10 @@ properties: phys: maxItems: 1 + phy-names: + items: + - const: pcie-phy + '#interrupt-cells': const: 1 diff --git a/dts/Bindings/pci/microchip,pcie-host.yaml b/dts/Bindings/pci/microchip,pcie-host.yaml index 7b07764571..edb4f81253 100644 --- a/dts/Bindings/pci/microchip,pcie-host.yaml +++ b/dts/Bindings/pci/microchip,pcie-host.yaml @@ -46,6 +46,24 @@ properties: msi-parent: description: MSI controller the device is capable of using. + interrupt-controller: + type: object + properties: + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + required: - reg - reg-names diff --git a/dts/Bindings/pci/sifive,fu740-pcie.yaml b/dts/Bindings/pci/sifive,fu740-pcie.yaml index 2b9d1d6fc6..392f0ab488 100644 --- a/dts/Bindings/pci/sifive,fu740-pcie.yaml +++ b/dts/Bindings/pci/sifive,fu740-pcie.yaml @@ -32,6 +32,8 @@ properties: - const: config - const: mgmt + dma-coherent: true + num-lanes: const: 8 @@ -61,10 +63,8 @@ required: - num-lanes - interrupts - interrupt-names - - interrupt-parent - interrupt-map-mask - interrupt-map - - clock-names - clocks - resets - pwren-gpios @@ -104,7 +104,6 @@ examples: <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; - clock-names = "pcie_aux"; clocks = <&prci PRCI_CLK_PCIE_AUX>; resets = <&prci 4>; pwren-gpios = <&gpio 5 0>; diff --git a/dts/Bindings/pci/snps,dw-pcie-ep.yaml b/dts/Bindings/pci/snps,dw-pcie-ep.yaml index b5935b1b15..e59059ab5b 100644 --- a/dts/Bindings/pci/snps,dw-pcie-ep.yaml +++ b/dts/Bindings/pci/snps,dw-pcie-ep.yaml @@ -64,16 +64,12 @@ properties: maxItems: 1 deprecated: true - max-functions: - $ref: /schemas/types.yaml#/definitions/uint32 - description: maximum number of functions that can be configured - required: - reg - reg-names - compatible -unevaluatedProperties: false +additionalProperties: true examples: - | diff --git a/dts/Bindings/pci/snps,dw-pcie.yaml b/dts/Bindings/pci/snps,dw-pcie.yaml index 9ed0dfba7f..a5345c4947 100644 --- a/dts/Bindings/pci/snps,dw-pcie.yaml +++ b/dts/Bindings/pci/snps,dw-pcie.yaml @@ -73,7 +73,7 @@ properties: does not specify it, the driver autodetects it. deprecated: true -unevaluatedProperties: false +additionalProperties: true required: - reg diff --git a/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml b/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml index 144cbcd60a..179ab08584 100644 --- a/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -79,7 +79,7 @@ required: - resets - reset-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/pci/ti,am65-pci-ep.yaml b/dts/Bindings/pci/ti,am65-pci-ep.yaml index 78c217d362..74195c1f52 100644 --- a/dts/Bindings/pci/ti,am65-pci-ep.yaml +++ b/dts/Bindings/pci/ti,am65-pci-ep.yaml @@ -32,8 +32,12 @@ properties: maxItems: 1 ti,syscon-pcie-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. - $ref: /schemas/types.yaml#/definitions/phandle interrupts: minItems: 1 @@ -65,9 +69,7 @@ examples: <0x5506000 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; - num-ib-windows = <16>; - num-ob-windows = <16>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; diff --git a/dts/Bindings/pci/ti,am65-pci-host.yaml b/dts/Bindings/pci/ti,am65-pci-host.yaml index 834dc1c174..a20dccbafd 100644 --- a/dts/Bindings/pci/ti,am65-pci-host.yaml +++ b/dts/Bindings/pci/ti,am65-pci-host.yaml @@ -29,16 +29,27 @@ properties: - const: config - const: atu + interrupts: + maxItems: 1 + power-domains: maxItems: 1 ti,syscon-pcie-id: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_device_id register offset within SYSCON description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID - $ref: /schemas/types.yaml#/definitions/phandle ti,syscon-pcie-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the SYSCON entry + - description: pcie_ctrl register offset within SYSCON description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. - $ref: /schemas/types.yaml#/definitions/phandle msi-map: true @@ -84,10 +95,9 @@ examples: #size-cells = <2>; ranges = <0x81000000 0 0 0x10020000 0 0x00010000>, <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-id = <&scm_conf 0x0210>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; - num-viewport = <16>; max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; diff --git a/dts/Bindings/pci/ti,j721e-pci-host.yaml b/dts/Bindings/pci/ti,j721e-pci-host.yaml index cc900202df..2115d5a3f0 100644 --- a/dts/Bindings/pci/ti,j721e-pci-host.yaml +++ b/dts/Bindings/pci/ti,j721e-pci-host.yaml @@ -60,6 +60,8 @@ properties: - const: fck - const: pcie_refclk + dma-coherent: true + vendor-id: const: 0x104c diff --git a/dts/Bindings/pci/xilinx-versal-cpm.yaml b/dts/Bindings/pci/xilinx-versal-cpm.yaml index a2bbc0eb72..32f4641085 100644 --- a/dts/Bindings/pci/xilinx-versal-cpm.yaml +++ b/dts/Bindings/pci/xilinx-versal-cpm.yaml @@ -55,7 +55,6 @@ required: - reg-names - "#interrupt-cells" - interrupts - - interrupt-parent - interrupt-map - interrupt-map-mask - bus-range |