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authorSascha Hauer <s.hauer@pengutronix.de>2017-03-10 08:56:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-03-10 08:56:15 +0100
commit957bb6b6bcebc4c36f5f284dfb58d489e81016c6 (patch)
tree593d098617017987daaf8ce339e0eb29ea09fdde /dts/Bindings/pci
parentcc2392cf4f2d5208be427e9ffdeafba192f05cbe (diff)
downloadbarebox-957bb6b6bcebc4c36f5f284dfb58d489e81016c6.tar.gz
dts: update to v4.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pci')
-rw-r--r--dts/Bindings/pci/hisilicon-pcie.txt37
-rw-r--r--dts/Bindings/pci/mvebu-pci.txt3
-rw-r--r--dts/Bindings/pci/pci-iommu.txt6
-rw-r--r--dts/Bindings/pci/rcar-pci.txt1
-rw-r--r--dts/Bindings/pci/rockchip-pcie.txt2
-rw-r--r--dts/Bindings/pci/samsung,exynos5440-pcie.txt29
6 files changed, 74 insertions, 4 deletions
diff --git a/dts/Bindings/pci/hisilicon-pcie.txt b/dts/Bindings/pci/hisilicon-pcie.txt
index 59c2f47..b7fa3b9 100644
--- a/dts/Bindings/pci/hisilicon-pcie.txt
+++ b/dts/Bindings/pci/hisilicon-pcie.txt
@@ -42,3 +42,40 @@ Hip05 Example (note that Hip06 is the same except compatible):
0x0 0 0 4 &mbigen_pcie 4 13>;
status = "ok";
};
+
+HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
+The properties and their meanings are identical to those described in
+host-generic-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-generic-pci.txt:
+
+- compatible : Must be "hisilicon,pcie-almost-ecam"
+
+- reg : Two entries: First the ECAM configuration space for any
+ other bus underneath the root bus. Second, the base
+ and size of the HiSilicon host bridge registers include
+ the RC's own config space.
+
+Example:
+ pcie0: pcie@a0090000 {
+ compatible = "hisilicon,pcie-almost-ecam";
+ reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */
+ <0 0xa0090000 0 0x10000>; /* host bridge registers */
+ bus-range = <0 31>;
+ msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
+ msi-map-mask = <0xffff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
+ 0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
+ 0x0 0 0 2 &mbigen_pcie0 650 4
+ 0x0 0 0 3 &mbigen_pcie0 650 4
+ 0x0 0 0 4 &mbigen_pcie0 650 4>;
+ status = "ok";
+ };
diff --git a/dts/Bindings/pci/mvebu-pci.txt b/dts/Bindings/pci/mvebu-pci.txt
index 08c716b..2de6f65 100644
--- a/dts/Bindings/pci/mvebu-pci.txt
+++ b/dts/Bindings/pci/mvebu-pci.txt
@@ -78,7 +78,8 @@ and the following optional properties:
multiple lanes. If this property is not found, we assume that the
value is 0.
- reset-gpios: optional gpio to PERST#
-- reset-delay-us: delay in us to wait after reset de-assertion
+- reset-delay-us: delay in us to wait after reset de-assertion, if not
+ specified will default to 100ms, as required by the PCIe specification.
Example:
diff --git a/dts/Bindings/pci/pci-iommu.txt b/dts/Bindings/pci/pci-iommu.txt
index 56c8296..0def586 100644
--- a/dts/Bindings/pci/pci-iommu.txt
+++ b/dts/Bindings/pci/pci-iommu.txt
@@ -32,17 +32,17 @@ PCI root complex
Optional properties
-------------------
-- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier
+- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
data.
The property is an arbitrary number of tuples of
(rid-base,iommu,iommu-base,length).
Any RID r in the interval [rid-base, rid-base + length) is associated with
- the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base).
+ the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
- iommu-map-mask: A mask to be applied to each Requester ID prior to being
- mapped to an iommu-specifier per the iommu-map property.
+ mapped to an IOMMU specifier per the iommu-map property.
Example (1)
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
index eee518d..34712d6 100644
--- a/dts/Bindings/pci/rcar-pci.txt
+++ b/dts/Bindings/pci/rcar-pci.txt
@@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
"renesas,pcie-r8a7791" for the R8A7791 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
+ "renesas,pcie-r8a7796" for the R8A7796 SoC;
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
diff --git a/dts/Bindings/pci/rockchip-pcie.txt b/dts/Bindings/pci/rockchip-pcie.txt
index 71aeda1..1453a73 100644
--- a/dts/Bindings/pci/rockchip-pcie.txt
+++ b/dts/Bindings/pci/rockchip-pcie.txt
@@ -43,6 +43,8 @@ Required properties:
- interrupt-map-mask and interrupt-map: standard PCI properties
Optional Property:
+- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
+ using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset gpio
- num-lanes: number of lanes to use
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
diff --git a/dts/Bindings/pci/samsung,exynos5440-pcie.txt b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d..7d3b094 100644
--- a/dts/Bindings/pci/samsung,exynos5440-pcie.txt
+++ b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
@@ -7,8 +7,19 @@ Required properties:
- compatible: "samsung,exynos5440-pcie"
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ (Registers for the phy controller are DEPRECATED.
+ Use the PHY framework.)
+- reg-names : First name should be set to "elbi".
+ And use the "config" instead of getting the confgiruation address space
+ from "ranges".
+ NOTE: When use the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+ Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+
+Other common properties refer to
+ Documentation/devicetree/binding/pci/designware-pcie.txt
Example:
@@ -54,6 +65,24 @@ SoC specific DT Entry:
num-lanes = <4>;
};
+With using PHY framework:
+ pcie_phy0: pcie-phy@270000 {
+ ...
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ reg-names = "phy", "block";
+ ...
+ };
+
+ pcie@290000 {
+ ...
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
+ phys = <&pcie_phy0>;
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000
+ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
+ ...
+ };
+
Board specific DT Entry:
pcie@290000 {