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authorSascha Hauer <s.hauer@pengutronix.de>2018-02-27 09:40:19 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2018-03-01 14:29:51 +0100
commita9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch)
tree35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/Bindings/pci
parent5ba0e42cb24afdf59d48930daf495c148312fc67 (diff)
downloadbarebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz
dts: update to v4.16-rc1
Also includeded: ARM: dts: am33xx: do not delete no longer existing clocks Several clocks are removed from the am33xx dts files with v4.16-rc1. Remove the corresponding /delete-node/ directives aswell to avoid dtc breakage. Also included: ARM: dts: imx6qdl: SolidRun: Fix upstream include Upstream dts file way renamed, so change include name accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pci')
-rw-r--r--dts/Bindings/pci/axis,artpec6-pcie.txt5
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-ep.txt22
-rw-r--r--dts/Bindings/pci/cdns,cdns-pcie-host.txt60
-rw-r--r--dts/Bindings/pci/fsl,imx6q-pcie.txt1
-rw-r--r--dts/Bindings/pci/samsung,exynos5440-pcie.txt58
5 files changed, 98 insertions, 48 deletions
diff --git a/dts/Bindings/pci/axis,artpec6-pcie.txt b/dts/Bindings/pci/axis,artpec6-pcie.txt
index 4e4aee4..979dc7b 100644
--- a/dts/Bindings/pci/axis,artpec6-pcie.txt
+++ b/dts/Bindings/pci/axis,artpec6-pcie.txt
@@ -4,7 +4,10 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
-- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
+ "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
+ "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
+ "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
- reg: base addresses and lengths of the PCIe controller (DBI),
the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
diff --git a/dts/Bindings/pci/cdns,cdns-pcie-ep.txt b/dts/Bindings/pci/cdns,cdns-pcie-ep.txt
new file mode 100644
index 0000000..9a30523
--- /dev/null
+++ b/dts/Bindings/pci/cdns,cdns-pcie-ep.txt
@@ -0,0 +1,22 @@
+* Cadence PCIe endpoint controller
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
+- reg: Should contain the controller register base address and AXI interface
+ region base address respectively.
+- reg-names: Must be "reg" and "mem" respectively.
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
+
+Optional properties:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+Example:
+
+pcie@fc000000 {
+ compatible = "cdns,cdns-pcie-ep";
+ reg = <0x0 0xfc000000 0x0 0x01000000>,
+ <0x0 0x80000000 0x0 0x40000000>;
+ reg-names = "reg", "mem";
+ cdns,max-outbound-regions = <16>;
+ max-functions = /bits/ 8 <8>;
+};
diff --git a/dts/Bindings/pci/cdns,cdns-pcie-host.txt b/dts/Bindings/pci/cdns,cdns-pcie-host.txt
new file mode 100644
index 0000000..20a33f3
--- /dev/null
+++ b/dts/Bindings/pci/cdns,cdns-pcie-host.txt
@@ -0,0 +1,60 @@
+* Cadence PCIe host controller
+
+This PCIe controller inherits the base properties defined in
+host-generic-pci.txt.
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
+- reg: Should contain the controller register base address, PCIe configuration
+ window base address, and AXI interface region base address respectively.
+- reg-names: Must be "reg", "cfg" and "mem" respectively.
+- #address-cells: Set to <3>
+- #size-cells: Set to <2>
+- device_type: Set to "pci"
+- ranges: Ranges for the PCI memory and I/O regions
+- #interrupt-cells: Set to <1>
+- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
+ mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
+ (default 32)
+- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
+ number of least significant bits kept during inbound (PCIe -> AXI) address
+ translations (default 32)
+- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
+- device-id: The PCI device ID (16 bits, default is design dependent)
+
+Example:
+
+pcie@fb000000 {
+ compatible = "cdns,cdns-pcie-host";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ linux,pci-domain = <0>;
+ cdns,max-outbound-regions = <16>;
+ cdns,no-bar-match-nbits = <32>;
+ vendor-id = /bits/ 16 <0x17cd>;
+ device-id = /bits/ 16 <0x0200>;
+
+ reg = <0x0 0xfb000000 0x0 0x01000000>,
+ <0x0 0x41000000 0x0 0x00001000>,
+ <0x0 0x40000000 0x0 0x04000000>;
+ reg-names = "reg", "cfg", "mem";
+
+ ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
+ <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
+
+ #interrupt-cells = <0x1>;
+
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
+ 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
+ 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
+
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+
+ msi-parent = <&its_pci>;
+};
diff --git a/dts/Bindings/pci/fsl,imx6q-pcie.txt b/dts/Bindings/pci/fsl,imx6q-pcie.txt
index 149d8f7..cb33421 100644
--- a/dts/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/dts/Bindings/pci/fsl,imx6q-pcie.txt
@@ -41,6 +41,7 @@ Optional properties:
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:
- "pcie_inbound_axi"
+- power-domains: Must be set to a phandle pointing to the PCIE_PHY power domain
Additional required properties for imx7d-pcie:
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
diff --git a/dts/Bindings/pci/samsung,exynos5440-pcie.txt b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bf..651d957 100644
--- a/dts/Bindings/pci/samsung,exynos5440-pcie.txt
+++ b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "samsung,exynos5440-pcie"
- reg: base addresses and lengths of the PCIe controller,
- the PHY controller, additional register for the PHY controller.
- (Registers for the PHY controller are DEPRECATED.
- Use the PHY framework.)
- reg-names : First name should be set to "elbi".
And use the "config" instead of getting the configuration address space
from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
Example:
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000
- 0x270000 0x1000
- 0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
- pcie@2a0000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
- clocks = <&clock 29>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
-With using PHY framework:
pcie_phy0: pcie-phy@270000 {
...
reg = <0x270000 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
};
pcie@290000 {
- ...
+ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x290000 0x1000>, <0x40000000 0x1000>;
reg-names = "elbi", "config";
+ clocks = <&clock 28>, <&clock 27>;
+ clock-names = "pcie", "pcie_bus";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
phys = <&pcie_phy0>;
ranges = <0x81000000 0 0 0x60001000 0 0x00010000
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
- ...
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <4>;
};
Board-specific DT Entry: