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authorSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-01-14 09:09:57 +0100
commit33fdc89d4cbd74aa54c28dc61d62972ab164e64d (patch)
treeda5ceff551dc1fdf2f2cc40e97a08035f9ef84fb /dts/Bindings/perf
parent13a52906ce67ed2ce67bfc10714934ffa6c5d646 (diff)
downloadbarebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.gz
barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.xz
dts: update to v5.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/perf')
-rw-r--r--dts/Bindings/perf/nds32v3-pmu.txt17
1 files changed, 17 insertions, 0 deletions
diff --git a/dts/Bindings/perf/nds32v3-pmu.txt b/dts/Bindings/perf/nds32v3-pmu.txt
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+++ b/dts/Bindings/perf/nds32v3-pmu.txt
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+* NDS32 Performance Monitor Units
+
+NDS32 core have a PMU for counting cpu and cache events like cache misses.
+The NDS32 PMU representation in the device tree should be done as under:
+
+Required properties:
+
+- compatible :
+ "andestech,nds32v3-pmu"
+
+- interrupts : The interrupt number for NDS32 PMU is 13.
+
+Example:
+pmu{
+ compatible = "andestech,nds32v3-pmu";
+ interrupts = <13>;
+}