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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:29:57 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-06-13 07:29:57 +0200 |
commit | a4f4bc65b33164eb8c19bcff9834cc87bcc845bb (patch) | |
tree | ef97762be5b614f160e9affddd1bbbec43c007dc /dts/Bindings/phy/rockchip-dp-phy.txt | |
parent | 83e61900b02965d01f0885e2db2077df35be7f56 (diff) | |
download | barebox-a4f4bc65b33164eb8c19bcff9834cc87bcc845bb.tar.gz barebox-a4f4bc65b33164eb8c19bcff9834cc87bcc845bb.tar.xz |
dts: update to v4.6-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/phy/rockchip-dp-phy.txt')
-rw-r--r-- | dts/Bindings/phy/rockchip-dp-phy.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/dts/Bindings/phy/rockchip-dp-phy.txt b/dts/Bindings/phy/rockchip-dp-phy.txt new file mode 100644 index 0000000000..50c4f9b00a --- /dev/null +++ b/dts/Bindings/phy/rockchip-dp-phy.txt @@ -0,0 +1,22 @@ +Rockchip specific extensions to the Analogix Display Port PHY +------------------------------------ + +Required properties: +- compatible : should be one of the following supported values: + - "rockchip.rk3288-dp-phy" +- clocks: from common clock binding: handle to dp clock. + of memory mapped region. +- clock-names: from common clock binding: + Required elements: "24m" +- rockchip,grf: phandle to the syscon managing the "general register files" +- #phy-cells : from the generic PHY bindings, must be 0; + +Example: + +edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; +}; |