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authorSascha Hauer <s.hauer@pengutronix.de>2016-02-03 10:25:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2016-02-04 08:40:36 +0100
commit0ff58575c9d66f660886387c2e68d8c5c724e87b (patch)
tree4a889d1478da83ae46db96f5c049872cdb90eeb6 /dts/Bindings/phy
parenta0da52f83c36a81984e0fca4b75d522b955df267 (diff)
downloadbarebox-0ff58575c9d66f660886387c2e68d8c5c724e87b.tar.gz
dts: update to v4.5-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/phy')
-rw-r--r--dts/Bindings/phy/brcm,brcmstb-sata-phy.txt1
-rw-r--r--dts/Bindings/phy/phy-ath79-usb.txt18
-rw-r--r--dts/Bindings/phy/phy-hi6220-usb.txt16
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt39
-rw-r--r--dts/Bindings/phy/rockchip-usb-phy.txt6
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt1
-rw-r--r--dts/Bindings/phy/ti-phy.txt20
7 files changed, 97 insertions, 4 deletions
diff --git a/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt b/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt
index 7f81ef9..d87ab7c 100644
--- a/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt
+++ b/dts/Bindings/phy/brcm,brcmstb-sata-phy.txt
@@ -2,6 +2,7 @@
Required properties:
- compatible: should be one or more of
+ "brcm,bcm7425-sata-phy"
"brcm,bcm7445-sata-phy"
"brcm,phy-sata3"
- address-cells: should be 1
diff --git a/dts/Bindings/phy/phy-ath79-usb.txt b/dts/Bindings/phy/phy-ath79-usb.txt
new file mode 100644
index 0000000..cafe219
--- /dev/null
+++ b/dts/Bindings/phy/phy-ath79-usb.txt
@@ -0,0 +1,18 @@
+* Atheros AR71XX/9XXX USB PHY
+
+Required properties:
+- compatible: "qca,ar7100-usb-phy"
+- #phys-cells: should be 0
+- reset-names: "usb-phy"[, "usb-suspend-override"]
+- resets: references to the reset controllers
+
+Example:
+
+ usb-phy {
+ compatible = "qca,ar7100-usb-phy";
+
+ reset-names = "usb-phy", "usb-suspend-override";
+ resets = <&rst 4>, <&rst 3>;
+
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/phy-hi6220-usb.txt b/dts/Bindings/phy/phy-hi6220-usb.txt
new file mode 100644
index 0000000..f17a56e
--- /dev/null
+++ b/dts/Bindings/phy/phy-hi6220-usb.txt
@@ -0,0 +1,16 @@
+Hisilicon hi6220 usb PHY
+-----------------------
+
+Required properties:
+- compatible: should be "hisilicon,hi6220-usb-phy"
+- #phy-cells: must be 0
+- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Example:
+ usb_phy: usbphy {
+ compatible = "hisilicon,hi6220-usb-phy";
+ #phy-cells = <0>;
+ phy-supply = <&fixed_5v_hub>;
+ hisilicon,peripheral-syscon = <&sys_ctrl>;
+ };
diff --git a/dts/Bindings/phy/rcar-gen3-phy-usb2.txt b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
new file mode 100644
index 0000000..2390e4e
--- /dev/null
+++ b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
@@ -0,0 +1,39 @@
+* Renesas R-Car generation 3 USB 2.0 PHY
+
+This file provides information on what the device node for the R-Car generation
+3 USB 2.0 PHY contains.
+
+Required properties:
+- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
+ SoC.
+- reg: offset and length of the partial USB 2.0 Host register block.
+- reg-names: must be "usb2_host".
+- clocks: clock phandle and specifier pair(s).
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
+
+Optional properties:
+To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
+combined, the device tree node should set HSUSB properties to reg and reg-names
+properties. This is because HSUSB has registers to select USB 2.0 host or
+peripheral at that channel:
+- reg: offset and length of the partial HSUSB register block.
+- reg-names: must be "hsusb".
+- interrupts: interrupt specifier for the PHY.
+
+Example (R-Car H3):
+
+ usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a7795";
+ reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
+ reg-names = "usb2_host", "hsusb";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
+ <&mstp7_clks R8A7795_CLK_HSUSB>;
+ };
+
+ usb-phy@ee0a0200 {
+ compatible = "renesas,usb2-phy-r8a7795";
+ reg = <0 0xee0a0200 0 0x700>;
+ reg-names = "usb2_host";
+ clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
+ };
diff --git a/dts/Bindings/phy/rockchip-usb-phy.txt b/dts/Bindings/phy/rockchip-usb-phy.txt
index 826454a..68498d5 100644
--- a/dts/Bindings/phy/rockchip-usb-phy.txt
+++ b/dts/Bindings/phy/rockchip-usb-phy.txt
@@ -1,7 +1,10 @@
ROCKCHIP USB2 PHY
Required properties:
- - compatible: rockchip,rk3288-usb-phy
+ - compatible: matching the soc type, one of
+ "rockchip,rk3066a-usb-phy"
+ "rockchip,rk3188-usb-phy"
+ "rockchip,rk3288-usb-phy"
- rockchip,grf : phandle to the syscon managing the "general
register files"
- #address-cells: should be 1
@@ -21,6 +24,7 @@ required properties:
Optional Properties:
- clocks : phandle + clock specifier for the phy clocks
- clock-names: string, clock name, must be "phyclk"
+- #clock-cells: for users of the phy-pll, should be 0
Example:
diff --git a/dts/Bindings/phy/sun4i-usb-phy.txt b/dts/Bindings/phy/sun4i-usb-phy.txt
index 0cebf74..95736d7 100644
--- a/dts/Bindings/phy/sun4i-usb-phy.txt
+++ b/dts/Bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-h3-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
diff --git a/dts/Bindings/phy/ti-phy.txt b/dts/Bindings/phy/ti-phy.txt
index 9cf9446..a3b3945 100644
--- a/dts/Bindings/phy/ti-phy.txt
+++ b/dts/Bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be "ti,omap-usb2"
+ Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
+ in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
@@ -40,10 +42,14 @@ Required properties:
* "wkupclk" - wakeup clock.
* "refclk" - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
@@ -77,14 +83,22 @@ Required properties:
* "div-clk" - apll clock
Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
- id: If there are multiple instance of the same type, in order to
differentiate between each instance "id" can be used (e.g., multi-lane PCIe
PHY). If "id" is not provided, it is set to default value of '1'.
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
+ register offset to write the PCS delay value.
+
+Deprecated properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+ the PHY.
+
+Recommended properies:
+ - syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
This is usually a subnode of ocp2scp to which it is connected.