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author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 09:15:32 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-06-08 10:41:39 +0200 |
commit | e54923b76e345080b73f3ae7f508657e5c63a9eb (patch) | |
tree | 8ea04209dd330c4a1257efade74fdda32bc7bb62 /dts/Bindings/phy | |
parent | d4fd877cc4c6439a806f9c5f1b8c561605ee1167 (diff) | |
download | barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.gz barebox-e54923b76e345080b73f3ae7f508657e5c63a9eb.tar.xz |
dts: update to v5.19-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/phy')
-rw-r--r-- | dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 12 | ||||
-rw-r--r-- | dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/phy/mixel,mipi-dsi-phy.txt | 29 | ||||
-rw-r--r-- | dts/Bindings/phy/mixel,mipi-dsi-phy.yaml | 107 | ||||
-rw-r--r-- | dts/Bindings/phy/qcom,qmp-phy.yaml | 4 | ||||
-rw-r--r-- | dts/Bindings/phy/renesas,usb2-phy.yaml | 1 | ||||
-rw-r--r-- | dts/Bindings/phy/socionext,uniphier-ahci-phy.yaml | 91 | ||||
-rw-r--r-- | dts/Bindings/phy/socionext,uniphier-pcie-phy.yaml | 47 | ||||
-rw-r--r-- | dts/Bindings/phy/socionext,uniphier-usb2-phy.yaml | 3 | ||||
-rw-r--r-- | dts/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 89 | ||||
-rw-r--r-- | dts/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 98 |
11 files changed, 382 insertions, 101 deletions
diff --git a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index d0b541a461..22636c9fda 100644 --- a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -37,6 +37,18 @@ properties: resets: maxItems: 1 + allwinner,direction: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + Direction of the D-PHY: + - "rx" for receiving (e.g. when used with MIPI CSI-2); + - "tx" for transmitting (e.g. when used with MIPI DSI). + + enum: + - tx + - rx + default: tx + required: - "#phy-cells" - compatible diff --git a/dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml b/dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml index 2437c36833..632d61c07f 100644 --- a/dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml +++ b/dts/Bindings/phy/marvell,armada-3700-utmi-phy.yaml @@ -45,7 +45,7 @@ additionalProperties: false examples: - | usb2_utmi_host_phy: phy@5f000 { - compatible = "marvell,armada-3700-utmi-host-phy"; + compatible = "marvell,a3700-utmi-host-phy"; reg = <0x5f000 0x800>; marvell,usb-misc-reg = <&usb2_syscon>; #phy-cells = <0>; diff --git a/dts/Bindings/phy/mixel,mipi-dsi-phy.txt b/dts/Bindings/phy/mixel,mipi-dsi-phy.txt deleted file mode 100644 index 9b23407233..0000000000 --- a/dts/Bindings/phy/mixel,mipi-dsi-phy.txt +++ /dev/null @@ -1,29 +0,0 @@ -Mixel DSI PHY for i.MX8 - -The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the -MIPI-DSI IP from Northwest Logic). It represents the physical layer for the -electrical signals for DSI. - -Required properties: -- compatible: Must be: - - "fsl,imx8mq-mipi-dphy" -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "phy_ref": phandle and specifier referring to the DPHY ref clock -- reg: the register range of the PHY controller -- #phy-cells: number of cells in PHY, as defined in - Documentation/devicetree/bindings/phy/phy-bindings.txt - this must be <0> - -Optional properties: -- power-domains: phandle to power domain - -Example: - dphy: dphy@30a0030 { - compatible = "fsl,imx8mq-mipi-dphy"; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - reg = <0x30a00300 0x100>; - power-domains = <&pd_mipi0>; - #phy-cells = <0>; - }; diff --git a/dts/Bindings/phy/mixel,mipi-dsi-phy.yaml b/dts/Bindings/phy/mixel,mipi-dsi-phy.yaml new file mode 100644 index 0000000000..786cfd71cb --- /dev/null +++ b/dts/Bindings/phy/mixel,mipi-dsi-phy.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel DSI PHY for i.MX8 + +maintainers: + - Guido Günther <agx@sigxcpu.org> + +description: | + The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the + MIPI-DSI IP from Northwest Logic). It represents the physical layer for the + electrical signals for DSI. + + The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work + in either MIPI-DSI PHY mode or LVDS PHY mode. + +properties: + compatible: + enum: + - fsl,imx8mq-mipi-dphy + - fsl,imx8qxp-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: phy_ref + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + "#phy-cells": + const: 0 + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - power-domains + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-mipi-dphy + then: + properties: + fsl,syscon: false + + required: + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-dphy + then: + properties: + assigned-clocks: false + assigned-clock-parents: false + assigned-clock-rates: false + + required: + - fsl,syscon + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mq-clock.h> + dphy: dphy@30a0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + reg = <0x30a00300 0x100>; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&pgc_mipi>; + }; diff --git a/dts/Bindings/phy/qcom,qmp-phy.yaml b/dts/Bindings/phy/qcom,qmp-phy.yaml index e20d9b087b..8b850c5ab1 100644 --- a/dts/Bindings/phy/qcom,qmp-phy.yaml +++ b/dts/Bindings/phy/qcom,qmp-phy.yaml @@ -39,6 +39,7 @@ properties: - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm6115-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy @@ -57,6 +58,7 @@ properties: - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy reg: minItems: 1 @@ -163,6 +165,7 @@ allOf: contains: enum: - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy then: properties: clocks: @@ -279,6 +282,7 @@ allOf: enum: - qcom,msm8998-qmp-ufs-phy - qcom,sdm845-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy diff --git a/dts/Bindings/phy/renesas,usb2-phy.yaml b/dts/Bindings/phy/renesas,usb2-phy.yaml index 16807bbbdc..f82649a55e 100644 --- a/dts/Bindings/phy/renesas,usb2-phy.yaml +++ b/dts/Bindings/phy/renesas,usb2-phy.yaml @@ -32,6 +32,7 @@ properties: - items: - enum: + - renesas,usb2-phy-r9a07g043 # RZ/G2UL - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} - renesas,usb2-phy-r9a07g054 # RZ/V2L - const: renesas,rzg2l-usb2-phy diff --git a/dts/Bindings/phy/socionext,uniphier-ahci-phy.yaml b/dts/Bindings/phy/socionext,uniphier-ahci-phy.yaml index 3b400a85b4..a3cd45acea 100644 --- a/dts/Bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/dts/Bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -30,32 +30,79 @@ properties: minItems: 1 maxItems: 2 - clock-names: - oneOf: - - items: # for PXs2 - - const: link - - items: # for Pro4 - - const: link - - const: gio - - items: # for others - - const: link - - const: phy + clock-names: true resets: minItems: 2 - maxItems: 5 + maxItems: 6 - reset-names: - oneOf: - - items: # for Pro4 - - const: link - - const: gio - - const: pm - - const: tx - - const: rx - - items: # for others - - const: link - - const: phy + reset-names: true + +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro4-ahci-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: gio + resets: + minItems: 6 + maxItems: 6 + reset-names: + items: + - const: link + - const: gio + - const: phy + - const: pm + - const: tx + - const: rx + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pxs2-ahci-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pxs3-ahci-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy required: - compatible diff --git a/dts/Bindings/phy/socionext,uniphier-pcie-phy.yaml b/dts/Bindings/phy/socionext,uniphier-pcie-phy.yaml index fbb71d6dd5..b3ed2f74a4 100644 --- a/dts/Bindings/phy/socionext,uniphier-pcie-phy.yaml +++ b/dts/Bindings/phy/socionext,uniphier-pcie-phy.yaml @@ -31,28 +31,51 @@ properties: minItems: 1 maxItems: 2 - clock-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for others + clock-names: true resets: minItems: 1 maxItems: 2 - reset-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for others + reset-names: true socionext,syscon: $ref: /schemas/types.yaml#/definitions/phandle description: A phandle to system control to set configurations for phy +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro5-pcie-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + else: + properties: + clocks: + maxItems: 1 + clock-names: + const: link + resets: + maxItems: 1 + reset-names: + const: link + required: - compatible - reg diff --git a/dts/Bindings/phy/socionext,uniphier-usb2-phy.yaml b/dts/Bindings/phy/socionext,uniphier-usb2-phy.yaml index 479b203f7a..63dab914a4 100644 --- a/dts/Bindings/phy/socionext,uniphier-usb2-phy.yaml +++ b/dts/Bindings/phy/socionext,uniphier-usb2-phy.yaml @@ -43,6 +43,9 @@ patternProperties: "#phy-cells": const: 0 + vbus-supply: + description: A phandle to the regulator for USB VBUS, only for USB host + required: - reg - "#phy-cells" diff --git a/dts/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/dts/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml index 33946efcac..21e4414eea 100644 --- a/dts/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/dts/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -31,27 +31,15 @@ properties: const: 0 clocks: - minItems: 1 + minItems: 2 maxItems: 3 - clock-names: - oneOf: - - const: link # for PXs2 - - items: # for PXs3 with phy-ext - - const: link - - const: phy - - const: phy-ext - - items: # for others - - const: link - - const: phy + clock-names: true resets: maxItems: 2 - reset-names: - items: - - const: link - - const: phy + reset-names: true vbus-supply: description: A phandle to the regulator for USB VBUS @@ -74,6 +62,77 @@ properties: required for each port, if any one is omitted, the trimming data of the port will not be set at all. +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro5-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs2-usb3-hsphy + - socionext,uniphier-ld20-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs3-usb3-hsphy + - socionext,uniphier-nx1-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + items: + - const: link + - const: phy + - const: phy-ext + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + required: - compatible - reg diff --git a/dts/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/dts/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 92d46eb913..4c26d2d230 100644 --- a/dts/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/dts/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -35,33 +35,88 @@ properties: minItems: 2 maxItems: 3 - clock-names: - oneOf: - - items: # for Pro4, Pro5 - - const: gio - - const: link - - items: # for PXs3 with phy-ext - - const: link - - const: phy - - const: phy-ext - - items: # for others - - const: link - - const: phy + clock-names: true resets: maxItems: 2 - reset-names: - oneOf: - - items: # for Pro4,Pro5 - - const: gio - - const: link - - items: # for others - - const: link - - const: phy + reset-names: true vbus-supply: - description: A phandle to the regulator for USB VBUS + description: A phandle to the regulator for USB VBUS, only for USB host + +allOf: + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pro4-usb3-ssphy + - socionext,uniphier-pro5-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs2-usb3-ssphy + - socionext,uniphier-ld20-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs3-usb3-ssphy + - socionext,uniphier-nx1-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + items: + - const: link + - const: phy + - const: phy-ext + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy required: - compatible @@ -71,7 +126,6 @@ required: - clock-names - resets - reset-names - - vbus-supply additionalProperties: false |