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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-23 12:14:59 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-05 20:49:06 +0200 |
commit | abef60363d8ecac66e45853f328afa8eeb9e00fd (patch) | |
tree | c7d6f1dcf0ef5154b9182da86f1acad048cb7da1 /dts/Bindings/pwm/imx-tpm-pwm.txt | |
parent | e307bc559a2830b7f695150212ea1b26cdca69fb (diff) | |
download | barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.gz barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.xz |
dts: update to v5.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm/imx-tpm-pwm.txt')
-rw-r--r-- | dts/Bindings/pwm/imx-tpm-pwm.txt | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/dts/Bindings/pwm/imx-tpm-pwm.txt b/dts/Bindings/pwm/imx-tpm-pwm.txt deleted file mode 100644 index 5bf20950a2..0000000000 --- a/dts/Bindings/pwm/imx-tpm-pwm.txt +++ /dev/null @@ -1,22 +0,0 @@ -Freescale i.MX TPM PWM controller - -Required properties: -- compatible : Should be "fsl,imx7ulp-pwm". -- reg: Physical base address and length of the controller's registers. -- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. -- clocks : The clock provided by the SoC to drive the PWM. -- interrupts: The interrupt for the PWM controller. - -Note: The TPM counter and period counter are shared between multiple channels, so all channels -should use same period setting. - -Example: - -tpm4: pwm@40250000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x40250000 0x1000>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - #pwm-cells = <3>; -}; |