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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-04-20 15:07:38 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-04-27 21:17:17 +0200 |
commit | 8d158e1a40917e48cb68131a6cfd1b8755a4d8a0 (patch) | |
tree | 76118ca8fbf736bbdbc30b9fa2480a0d2a775597 /dts/Bindings/pwm | |
parent | 15d46bac2280def447c7fd74686d44d938c24556 (diff) | |
download | barebox-8d158e1a40917e48cb68131a6cfd1b8755a4d8a0.tar.gz barebox-8d158e1a40917e48cb68131a6cfd1b8755a4d8a0.tar.xz |
dts: update to v5.7-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
-rw-r--r-- | dts/Bindings/pwm/google,cros-ec-pwm.txt | 23 | ||||
-rw-r--r-- | dts/Bindings/pwm/google,cros-ec-pwm.yaml | 40 | ||||
-rw-r--r-- | dts/Bindings/pwm/iqs620a-pwm.yaml | 32 | ||||
-rw-r--r-- | dts/Bindings/pwm/nvidia,tegra20-pwm.txt | 1 | ||||
-rw-r--r-- | dts/Bindings/pwm/pwm-mediatek.txt | 5 | ||||
-rw-r--r-- | dts/Bindings/pwm/renesas,tpu-pwm.yaml | 4 |
6 files changed, 82 insertions, 23 deletions
diff --git a/dts/Bindings/pwm/google,cros-ec-pwm.txt b/dts/Bindings/pwm/google,cros-ec-pwm.txt deleted file mode 100644 index 472bd46ab5..0000000000 --- a/dts/Bindings/pwm/google,cros-ec-pwm.txt +++ /dev/null @@ -1,23 +0,0 @@ -* PWM controlled by ChromeOS EC - -Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller -(EC) and controlled via a host-command interface. - -An EC PWM node should be only found as a sub-node of the EC node (see -Documentation/devicetree/bindings/mfd/cros-ec.txt). - -Required properties: -- compatible: Must contain "google,cros-ec-pwm" -- #pwm-cells: Should be 1. The cell specifies the PWM index. - -Example: - cros-ec@0 { - compatible = "google,cros-ec-spi"; - - ... - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - }; diff --git a/dts/Bindings/pwm/google,cros-ec-pwm.yaml b/dts/Bindings/pwm/google,cros-ec-pwm.yaml new file mode 100644 index 0000000000..24c217b765 --- /dev/null +++ b/dts/Bindings/pwm/google,cros-ec-pwm.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM controlled by ChromeOS EC + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>' + +description: | + Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller + (EC) and controlled via a host-command interface. + An EC PWM node should be only found as a sub-node of the EC node (see + Documentation/devicetree/bindings/mfd/cros-ec.txt). + +properties: + compatible: + const: google,cros-ec-pwm + "#pwm-cells": + description: The cell specifies the PWM index. + const: 1 + +required: + - compatible + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + cros-ec@0 { + compatible = "google,cros-ec-spi"; + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + }; diff --git a/dts/Bindings/pwm/iqs620a-pwm.yaml b/dts/Bindings/pwm/iqs620a-pwm.yaml new file mode 100644 index 0000000000..1d7c27be50 --- /dev/null +++ b/dts/Bindings/pwm/iqs620a-pwm.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/iqs620a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS620A PWM Generator + +maintainers: + - Jeff LaBundy <jeff@labundy.com> + +description: | + The Azoteq IQS620A multi-function sensor generates a fixed-frequency PWM + output represented by a "pwm" child node from the parent MFD driver. See + Documentation/devicetree/bindings/mfd/iqs62x.yaml for further details as + well as an example. + +properties: + compatible: + enum: + - azoteq,iqs620a-pwm + + "#pwm-cells": + const: 2 + +required: + - compatible + - "#pwm-cells" + +additionalProperties: false + +... diff --git a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt index 0a69eadf44..74c41e34c3 100644 --- a/dts/Bindings/pwm/nvidia,tegra20-pwm.txt +++ b/dts/Bindings/pwm/nvidia,tegra20-pwm.txt @@ -9,6 +9,7 @@ Required properties: - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 - "nvidia,tegra186-pwm": for Tegra186 + - "nvidia,tegra194-pwm": for Tegra194 - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of the cells format. diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt index 95536d83c5..29adff59c4 100644 --- a/dts/Bindings/pwm/pwm-mediatek.txt +++ b/dts/Bindings/pwm/pwm-mediatek.txt @@ -19,10 +19,15 @@ Required properties: - "pwm1-8": the eight per PWM clocks for mt2712 - "pwm1-6": the six per PWM clocks for mt7622 - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1" : the PWM1 clock for mt7629 - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. +Optional properties: +- assigned-clocks: Reference to the PWM clock entries. +- assigned-clock-parents: The phandle of the parent clock of PWM clock. + Example: pwm0: pwm@11006000 { compatible = "mediatek,mt7623-pwm"; diff --git a/dts/Bindings/pwm/renesas,tpu-pwm.yaml b/dts/Bindings/pwm/renesas,tpu-pwm.yaml index 4969a95499..4bf62a3d5b 100644 --- a/dts/Bindings/pwm/renesas,tpu-pwm.yaml +++ b/dts/Bindings/pwm/renesas,tpu-pwm.yaml @@ -19,6 +19,10 @@ properties: - renesas,tpu-r8a7744 # RZ/G1N - renesas,tpu-r8a7745 # RZ/G1E - renesas,tpu-r8a7790 # R-Car H2 + - renesas,tpu-r8a7791 # R-Car M2-W + - renesas,tpu-r8a7792 # R-Car V2H + - renesas,tpu-r8a7793 # R-Car M2-N + - renesas,tpu-r8a7794 # R-Car E2 - renesas,tpu-r8a7795 # R-Car H3 - renesas,tpu-r8a7796 # R-Car M3-W - renesas,tpu-r8a77965 # R-Car M3-N |