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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-04 11:21:58 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-11-04 11:21:58 +0100 |
| commit | a10a5d019acc203c2ab531104788e4e053578e21 (patch) | |
| tree | 0011860c7339972ae08f994aed4dd1d94e58fcee /dts/Bindings/pwm | |
| parent | 604ad71929a1deabe77b7ab9c3655d82002d79c9 (diff) | |
| download | barebox-a10a5d019acc203c2ab531104788e4e053578e21.tar.gz barebox-a10a5d019acc203c2ab531104788e4e053578e21.tar.xz | |
dts: update to v3.18-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
| -rw-r--r-- | dts/Bindings/pwm/pwm-fsl-ftm.txt | 19 | ||||
| -rw-r--r-- | dts/Bindings/pwm/pwm-rockchip.txt | 4 |
2 files changed, 20 insertions, 3 deletions
diff --git a/dts/Bindings/pwm/pwm-fsl-ftm.txt b/dts/Bindings/pwm/pwm-fsl-ftm.txt index 0bda229a61..3899d6a557 100644 --- a/dts/Bindings/pwm/pwm-fsl-ftm.txt +++ b/dts/Bindings/pwm/pwm-fsl-ftm.txt @@ -1,5 +1,20 @@ Freescale FlexTimer Module (FTM) PWM controller +The same FTM PWM device can have a different endianness on different SoCs. The +device tree provides a property to describing this so that an operating system +device driver can handle all variants of the device. Refer to the table below +for the endianness of the FTM PWM block as integrated into the existing SoCs: + + SoC | FTM-PWM endianness + --------+------------------- + Vybrid | LE + LS1 | BE + LS2 | LE + +Please see ../regmap/regmap.txt for more detail about how to specify endian +modes in device tree. + + Required properties: - compatible: Should be "fsl,vf610-ftm-pwm". - reg: Physical base address and length of the controller's registers @@ -16,7 +31,8 @@ Required properties: - pinctrl-names: Must contain a "default" entry. - pinctrl-NNN: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. - +- big-endian: Boolean property, required if the FTM PWM registers use a big- + endian rather than little-endian layout. Example: @@ -32,4 +48,5 @@ pwm0: pwm@40038000 { <&clks VF610_CLK_FTM0_EXT_FIX_EN>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_1>; + big-endian; }; diff --git a/dts/Bindings/pwm/pwm-rockchip.txt b/dts/Bindings/pwm/pwm-rockchip.txt index d47d15a6a2..b8be3d09ee 100644 --- a/dts/Bindings/pwm/pwm-rockchip.txt +++ b/dts/Bindings/pwm/pwm-rockchip.txt @@ -7,8 +7,8 @@ Required properties: "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: phandle and clock specifier of the PWM reference clock - - #pwm-cells: should be 2. See pwm.txt in this directory for a - description of the cell format. + - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory + for a description of the cell format. Example: |