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authorSascha Hauer <s.hauer@pengutronix.de>2022-08-24 08:46:04 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2022-08-25 15:39:39 +0200
commiteddd8312948329e28f00a6f1ca52b3e7f3c330ee (patch)
tree1b4ef77f92f72af55f853e09be1789a4206fbcb6 /dts/Bindings/pwm
parenteed776a50f486d4c1951da32a30d3fd1588ac6e2 (diff)
downloadbarebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.gz
barebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.xz
dts: update to v6.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
-rw-r--r--dts/Bindings/pwm/clk-pwm.yaml46
-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt3
2 files changed, 49 insertions, 0 deletions
diff --git a/dts/Bindings/pwm/clk-pwm.yaml b/dts/Bindings/pwm/clk-pwm.yaml
new file mode 100644
index 0000000000..ec17682915
--- /dev/null
+++ b/dts/Bindings/pwm/clk-pwm.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/clk-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock based PWM controller
+
+maintainers:
+ - Nikita Travkin <nikita@trvn.ru>
+
+description: |
+ Some systems have clocks that can be exposed to external devices.
+ (e.g. by muxing them to GPIO pins)
+ It's often possible to control duty-cycle of such clocks which makes them
+ suitable for generating PWM signal.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: clk-pwm
+
+ clocks:
+ description: Clock used to generate the signal.
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - clocks
+
+examples:
+ - |
+ pwm {
+ compatible = "clk-pwm";
+ #pwm-cells = <2>;
+ clocks = <&gcc 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_clk_flash_default>;
+ };
diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt
index 033d1fc0f4..554c96b6d0 100644
--- a/dts/Bindings/pwm/pwm-mediatek.txt
+++ b/dts/Bindings/pwm/pwm-mediatek.txt
@@ -9,6 +9,8 @@ Required properties:
- "mediatek,mt7628-pwm": found on mt7628 SoC.
- "mediatek,mt7629-pwm": found on mt7629 SoC.
- "mediatek,mt8183-pwm": found on mt8183 SoC.
+ - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
+ - "mediatek,mt8365-pwm": found on mt8365 SoC.
- "mediatek,mt8516-pwm": found on mt8516 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
@@ -18,6 +20,7 @@ Required properties:
has no clocks
- "top": the top clock generator
- "main": clock used by the PWM core
+ - "pwm1-3": the three per PWM clocks for mt8365
- "pwm1-8": the eight per PWM clocks for mt2712
- "pwm1-6": the six per PWM clocks for mt7622
- "pwm1-5": the five per PWM clocks for mt7623