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authorSascha Hauer <s.hauer@pengutronix.de>2021-03-09 14:49:17 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2021-03-17 09:37:13 +0100
commitf826d85b7ab0924d5bf1a5458c49e7f7d8207a23 (patch)
treedd6354e00da0aa143d1db6164e1a455dddb9b892 /dts/Bindings/pwm
parent0e37f94fbe1bd189f35b3e1718549ec2f4a710ee (diff)
downloadbarebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.gz
barebox-f826d85b7ab0924d5bf1a5458c49e7f7d8207a23.tar.xz
dts: update to v5.12-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/pwm')
-rw-r--r--dts/Bindings/pwm/pwm-sifive.yaml9
-rw-r--r--dts/Bindings/pwm/pwm-zx.txt22
2 files changed, 6 insertions, 25 deletions
diff --git a/dts/Bindings/pwm/pwm-sifive.yaml b/dts/Bindings/pwm/pwm-sifive.yaml
index 5ac25275d8..84e66913d0 100644
--- a/dts/Bindings/pwm/pwm-sifive.yaml
+++ b/dts/Bindings/pwm/pwm-sifive.yaml
@@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- - const: sifive,fu540-c000-pwm
+ - enum:
+ - sifive,fu540-c000-pwm
+ - sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
- compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
- as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ compatible strings are "sifive,fu540-c000-pwm" and
+ "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
+ SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.
diff --git a/dts/Bindings/pwm/pwm-zx.txt b/dts/Bindings/pwm/pwm-zx.txt
deleted file mode 100644
index 3c8fe7aa82..0000000000
--- a/dts/Bindings/pwm/pwm-zx.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-ZTE ZX PWM controller
-
-Required properties:
- - compatible: Should be "zte,zx296718-pwm".
- - reg: Physical base address and length of the controller's registers.
- - clocks : The phandle and specifier referencing the controller's clocks.
- - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
- PCLK is for register access, while WCLK is the reference clock for
- calculating period and duty cycles.
- - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
- the cells format.
-
-Example:
-
- pwm: pwm@1439000 {
- compatible = "zte,zx296718-pwm";
- reg = <0x1439000 0x1000>;
- clocks = <&lsp1crm LSP1_PWM_PCLK>,
- <&lsp1crm LSP1_PWM_WCLK>;
- clock-names = "pclk", "wclk";
- #pwm-cells = <3>;
- };