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authorSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
commitbfbf18d991756858337f7700e8ff0a6f0dc31afc (patch)
treecf3568de4fdff1891e277507f08f49a871682706 /dts/Bindings/reset/uniphier-reset.txt
parent834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff)
downloadbarebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/reset/uniphier-reset.txt')
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diff --git a/dts/Bindings/reset/uniphier-reset.txt b/dts/Bindings/reset/uniphier-reset.txt
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+UniPhier reset controller
+
+
+System reset
+------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sld3-reset" - for PH1-sLD3 SoC.
+ "socionext,uniphier-ld4-reset" - for PH1-LD4 SoC.
+ "socionext,uniphier-pro4-reset" - for PH1-Pro4 SoC.
+ "socionext,uniphier-sld8-reset" - for PH1-sLD8 SoC.
+ "socionext,uniphier-pro5-reset" - for PH1-Pro5 SoC.
+ "socionext,uniphier-pxs2-reset" - for ProXstream2/PH1-LD6b SoC.
+ "socionext,uniphier-ld11-reset" - for PH1-LD11 SoC.
+ "socionext,uniphier-ld20-reset" - for PH1-LD20 SoC.
+- #reset-cells: should be 1.
+
+Example:
+
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-ld20-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ reset {
+ compatible = "socionext,uniphier-ld20-reset";
+ #reset-cells = <1>;
+ };
+
+ other nodes ...
+ };
+
+
+Media I/O (MIO) reset
+---------------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sld3-mio-reset" - for PH1-sLD3 SoC.
+ "socionext,uniphier-ld4-mio-reset" - for PH1-LD4 SoC.
+ "socionext,uniphier-pro4-mio-reset" - for PH1-Pro4 SoC.
+ "socionext,uniphier-sld8-mio-reset" - for PH1-sLD8 SoC.
+ "socionext,uniphier-pro5-mio-reset" - for PH1-Pro5 SoC.
+ "socionext,uniphier-pxs2-mio-reset" - for ProXstream2/PH1-LD6b SoC.
+ "socionext,uniphier-ld11-mio-reset" - for PH1-LD11 SoC.
+ "socionext,uniphier-ld20-mio-reset" - for PH1-LD20 SoC.
+- #reset-cells: should be 1.
+
+Example:
+
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-ld20-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ reset {
+ compatible = "socionext,uniphier-ld20-mio-reset";
+ #reset-cells = <1>;
+ };
+
+ other nodes ...
+ };
+
+
+Peripheral reset
+----------------
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-ld4-peri-reset" - for PH1-LD4 SoC.
+ "socionext,uniphier-pro4-peri-reset" - for PH1-Pro4 SoC.
+ "socionext,uniphier-sld8-peri-reset" - for PH1-sLD8 SoC.
+ "socionext,uniphier-pro5-peri-reset" - for PH1-Pro5 SoC.
+ "socionext,uniphier-pxs2-peri-reset" - for ProXstream2/PH1-LD6b SoC.
+ "socionext,uniphier-ld11-peri-reset" - for PH1-LD11 SoC.
+ "socionext,uniphier-ld20-peri-reset" - for PH1-LD20 SoC.
+- #reset-cells: should be 1.
+
+Example:
+
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-ld20-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ reset {
+ compatible = "socionext,uniphier-ld20-peri-reset";
+ #reset-cells = <1>;
+ };
+
+ other nodes ...
+ };