dts: update to v3.16-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 34 insertions, 0 deletions

diff --git a/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt b/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt
new file mode 100644
index 0000000000..c8f7757148
--- /dev/null
+++ b/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt
@@ -0,0 +1,21 @@
+Allwinner sunxi Peripheral Reset Controller
+===========================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be one of the following:
+  "allwinner,sun6i-a31-ahb1-reset"
+  "allwinner,sun6i-a31-clock-reset"
+- reg: should be register base and length as documented in the
+  datasheet
+- #reset-cells: 1, see below
+
+example:
+
+ahb1_rst: reset@01c202c0 {
+	#reset-cells = <1>;
+	compatible = "allwinner,sun6i-a31-ahb1-reset";
+	reg = <0x01c202c0 0xc>;
+};
diff --git a/dts/Bindings/reset/socfpga-reset.txt b/dts/Bindings/reset/socfpga-reset.txt
new file mode 100644
index 0000000000..32c1c8bfd5
--- /dev/null
+++ b/dts/Bindings/reset/socfpga-reset.txt
@@ -0,0 +1,13 @@
+Altera SOCFPGA Reset Manager
+
+Required properties:
+- compatible : "altr,rst-mgr"
+- reg : Should contain 1 register ranges(address and length)
+- #reset-cells: 1
+
+Example:
+	 rstmgr@ffd05000 {
+		#reset-cells = <1>;
+		compatible = "altr,rst-mgr";
+		reg = <0xffd05000 0x1000>;
+	};