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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-06-23 12:14:59 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-07-05 20:49:06 +0200 |
| commit | abef60363d8ecac66e45853f328afa8eeb9e00fd (patch) | |
| tree | c7d6f1dcf0ef5154b9182da86f1acad048cb7da1 /dts/Bindings/reset | |
| parent | e307bc559a2830b7f695150212ea1b26cdca69fb (diff) | |
| download | barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.gz barebox-abef60363d8ecac66e45853f328afa8eeb9e00fd.tar.xz | |
dts: update to v5.8-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/reset')
| -rw-r--r-- | dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml | 4 | ||||
| -rw-r--r-- | dts/Bindings/reset/fsl,imx7-src.txt | 6 | ||||
| -rw-r--r-- | dts/Bindings/reset/intel,rcu-gw.yaml | 3 | ||||
| -rw-r--r-- | dts/Bindings/reset/renesas,rst.yaml | 1 |
4 files changed, 10 insertions, 4 deletions
diff --git a/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml index 512a33bdb2..dfce6738b0 100644 --- a/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml +++ b/dts/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -7,7 +7,9 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: BCM7216 RESCAL reset controller -description: This document describes the BCM7216 RESCAL reset controller which is responsible for controlling the reset of the SATA and PCIe0/1 instances on BCM7216. +description: This document describes the BCM7216 RESCAL reset controller + which is responsible for controlling the reset of the SATA and PCIe0/1 + instances on BCM7216. maintainers: - Florian Fainelli <f.fainelli@gmail.com> diff --git a/dts/Bindings/reset/fsl,imx7-src.txt b/dts/Bindings/reset/fsl,imx7-src.txt index c2489e41a8..e10502d915 100644 --- a/dts/Bindings/reset/fsl,imx7-src.txt +++ b/dts/Bindings/reset/fsl,imx7-src.txt @@ -9,6 +9,8 @@ Required properties: - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon" - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon" - For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon" + - For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon" + - For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon" - reg: should be register base and length as documented in the datasheet - interrupts: Should contain SRC interrupt @@ -49,4 +51,6 @@ Example: For list of all valid reset indices see <dt-bindings/reset/imx7-reset.h> for i.MX7, <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM +<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and +<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and +<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP diff --git a/dts/Bindings/reset/intel,rcu-gw.yaml b/dts/Bindings/reset/intel,rcu-gw.yaml index 8ac4372826..6b2d56cc3f 100644 --- a/dts/Bindings/reset/intel,rcu-gw.yaml +++ b/dts/Bindings/reset/intel,rcu-gw.yaml @@ -21,8 +21,7 @@ properties: intel,global-reset: description: Global reset register offset and bit offset. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array items: - description: Register offset - description: Register bit offset diff --git a/dts/Bindings/reset/renesas,rst.yaml b/dts/Bindings/reset/renesas,rst.yaml index b5de1d196a..4c2b429ac7 100644 --- a/dts/Bindings/reset/renesas,rst.yaml +++ b/dts/Bindings/reset/renesas,rst.yaml @@ -23,6 +23,7 @@ description: | properties: compatible: enum: + - renesas,r8a7742-rst # RZ/G1H - renesas,r8a7743-rst # RZ/G1M - renesas,r8a7744-rst # RZ/G1N - renesas,r8a7745-rst # RZ/G1E |